United Microelectronics Corp.

Hsin-Liang Liu

Chin-Fu Lin

Shih-Yin Hsiao

Ke-Feng Lin

Chun-Hung Cheng

Yau-Kae Sheu

Yu-Chieh Lin

Shu-Wen Lin

Liang-An Huang

Yu-Chun Huang

Yuan-Cheng Yang

Chang-Lin Chen

Yu-Ciao Lin

A method for forming a gate oxide layer on a substrate is provided, in which a region of the substrate is defined out by a shallow trench isolation (STI) structure. An oxide layer covers over the substrate and a mask layer with an opening to expose oxide layer corresponding to the region with an interface edge of the STI structure. The method includes forming a silicon spacer on a sidewall of the opening. A cleaning process is performed through the opening to expose the substrate at the region. An oxidation process is performed on the substrate at the region to form the gate oxide layer, wherein the silicon spacer is also oxidized to merge to an edge of the gate oxide layer.

Gate oxide structure and method for fabricating the same

A fabricating method of a shallow trench isolation structure includes the following steps. Firstly, a substrate is provided, wherein a high voltage device area is defined in the substrate. Then, a first etching process is performed to partially remove the substrate, thereby forming a preliminary shallow trench in the high voltage device area. Then, a second etching process is performed to further remove the substrate corresponding to the preliminary shallow trench, thereby forming a first shallow trench in the high voltage device area. Afterwards, a dielectric material is filled in the first shallow trench, thereby forming a first shallow trench isolation structure.

Fabricating method of shallow trench isolation structure

Growing community of inventors

Tainan, Taiwan

Hsin-Liang Liu