Megica Corporation

Qualcomm Incorporated

Megit Acquisition Corp.

Hsin-Jung Lo

Mou-Shiung Lin

Chiu-Ming Chou

Chien-Kang Chou

Shih-Hsiung Lin

Jin-Yuan Lee

Ke-Hung Chen

Ying-Chih Chen

Ping-Jung Yang

Ching-San Lin

Te-Sheng Liu

Huei-Mei Yen

Li-Ren Lin

Shih Hsiung Lin

Integrated circuit chips and chip packages are disclosed that include an over-passivation scheme at a top of the integrated circuit chip and a bottom scheme at a bottom of the integrated circuit chip using a top post-passivation technology and a bottom structure technology. The integrated circuit chips can be connected to an external circuit or structure, such as ball-grid-array (BGA) substrate, printed circuit board, semiconductor chip, metal substrate, glass substrate or ceramic substrate, through the over-passivation scheme or the bottom scheme. Related fabrication techniques are described.

Integrated circuit chip using top post-passivation technology and bottom structure technology

A chip package includes a semiconductor substrate, a first metal pad over the semiconductor substrate, and a second metal pad over the semiconductor substrate. In a case, the first metal pad is tape automated bonded thereto, and the second metal pad is solder bonded thereto. In another case, the first metal pad is tape automated bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is solder bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is solder bonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is wirebonded thereto.

Chip package and method for fabricating the same

A device is described which includes a waveguide structure for signal transmission and power/ground delivery The waveguide structure includes a signal transmission part for transmitting an optical signal from an illuminant device to a detector. The signal transmission part may include transparent polymer, diamond or glass. The signal transmission part is used for a waveguide. The waveguide structure further includes a power/ground delivery part surrounding the signal transmission part. The power/ground delivery part is composed of at least one metal layer. Thus, the waveguide structure can provide an optical-signal transmission with high speed and high volume through the signal transmission part, while a stable power or ground reference can be provided to multiple units through the power/ground delivery part.

Waveguide structures for signal and/or power transmission in a semiconductor device

The present invention proposes a circuit component structure, which comprises a semiconductor substrate, a fine-line metallization structure formed over the semiconductor substrate and having at least one metal pad, a passivation layer formed over the fine-line metallization structure with the metal pads exposed by the openings of the passivation layer, at least one carbon nanotube layer formed over the fine-line metallization structure and the passivation layer and connecting with the metal pads. The present invention is to provide a carbon nanotube circuit component structure and a method for fabricating the same, wherein the circuit of a semiconductor element is made of an electrically conductive carbon nanotube, and the circuit of the semiconductor element can thus be made finer and denser via the superior electric conductivity, flexibility and strength of the carbon nanotube.

Carbon nanotube circuit component structure

A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate.

Stacked chip package with redistribution lines

A circuitry component comprising a semiconductor substrate, a pad over said semiconductor substrate, a tantalum-containing layer on a side wall and a bottom surface of said pad, a passivation layer over said semiconductor substrate, an opening in said passivation layer exposing said pad, a titanium-containing layer over said pad exposed by said opening, and a gold layer over said titanium-containing layer.

Metal pad or metal bump over pad exposed by passivation layer

A chip package includes a bump connecting said semiconductor chip and said circuitry component, wherein the semiconductor chip has a photosensitive area used to sense light. The chip package may include a ring-shaped protrusion connecting a transparent substrate and the semiconductor chip.

Chip package

This invention provides a wire bonding method, comprising providing an integrated circuit (IC) die having thereon a passivation layer and a plurality of first bonding pads exposed by respective openings in the passivation layer; forming a polymer layer on the passivation layer; forming an adhesive/barrier layer on the polymer layer; forming a metal pad layer on the adhesive/barrier layer; bonding a wire onto the metal pad layer to form a ball bond thereon; and after forming the ball bond on the metal pad layer, running the wire so as to contact the wire with a second bonding pad and forming a wedge bond thereto.

Wire bonding method for preventing polymer cracking

The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

Semiconductor chip with post-passivation scheme formed over passivation layer

A semiconductor chip comprises a metal pad exposed by an opening in a passivation layer, wherein the metal pad has a testing area and a bond area. During a step of testing, a testing probe contacts with the testing area for electrical testing. After the step of testing, a polymer layer is formed on the testing area with a probe mark created by the testing probe. Alternatively, a semiconductor chip comprises a testing pad and a bond pad respectively exposed by two openings in a passivation layer, wherein the testing pad is connected to the bond pad. During a step of testing, a testing probe contacts with the testing pad for electrical testing. After the step of testing, a polymer layer is formed on the testing pad with a probe mark created by the testing probe.

Semiconductor chip with a bonding pad having contact and test areas

A bonding process includes the following process. A bump is formed on a first electric device. A patterned insulation layer is formed on a second electric device, wherein the patterned insulation layer has a thickness between 5 &#x3bc;m and 400 &#x3bc;m, and an opening is in the patterned insulation layer and exposes the second electric device. The bump is joined to the second electric device exposed by the opening in the patterned insulation layer.

Process of bonding circuitry components

A chip assembly includes a semiconductor chip, a bump and an external circuit. The semiconductor chip includes a semiconductor substrate, a transistor in and on the semiconductor substrate, multiple dielectric layers over the semiconductor substrate, a metallization structure over the semiconductor substrate, wherein the metallization structure is connected to the transistor, and a passivation layer over the metallization structure, over the dielectric layers and over the transistor. The bump is connected to the metallization structure through an opening in the passivation layer, wherein the bump includes an adhesion/barrier layer and a gold layer over the adhesion/barrier layer. The external circuit can be connected to the bump using a tape carrier package (TCP), a chip-on-film (COF) package or a chip-on-glass (COG) assembly.

Chip assembly with interconnection by metal bump

A semiconductor chip includes first, second and third metal interconnects and an insulating layer over a semiconductor substrate. First, second and third openings in the insulating layer are over first, second and third contact points of the first, second and third metal interconnects, respectively. A fourth metal interconnect over the insulating layer connects the first and second contact points. The fourth metal interconnect includes a first metal layer and a second metal layer. The first metal layer is under but not at a sidewall of the second metal layer. The semiconductor chip includes a metal bump connected to the third contact point through the third opening, and a dielectric layer over the fourth metal interconnect and the insulating layer. No opening is in the dielectric layer on the fourth metal interconnect, and the metal bump has a top higher than a top surface of the dielectric layer.

Chip structure

A bonding pad structure is fabricated on an integrated circuit (IC) substrate having at least a contact layer on its top surface. A passivation layer covers the top surface of the IC substrate and the contact layer. The passivation layer has an opening exposing a portion of the contact layer. An electrically conductive adhesion/barrier layer directly is bonded to the contact layer. The electrically conductive adhesion/barrier layer extends to a top surface of the passivation layer. A bonding metal layer is stacked on the electrically conductive adhesion/barrier layer.

Growing community of inventors

Taipei County, Taiwan

Hsin-Jung Lo