United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

Hsin-Fu Huang

Chi-Mao Hsu

Min-Chuan Tsai

Chin-Fu Lin

Tsun-Min Cheng

Pin-Hong Chen

Chien-Hao Chen

Wei-Yu Chen

Kuo-Chih Lai

Chun-Chieh Chiu

Li-Han Chen

Wei-Chuan Tsai

Yi-Wei Chen

Kun-Hsien Lin

Yen-Tsai Yi

Chi-Yuan Sun

Chun-Yuan Wu

Nien-Ting Ho

Chih-Chieh Tsai

Tzu-Chieh Chen

Shih-Fang Tzou

Chia-Chang Hsu

Tzung-Ying Lee

Shih-Min Chou

Kuo-Chin Hung

Wei-Ming Hsiao

Hsiang-Wen Ke

Jin-Yan Chiou

Shu Min Huang

Ya-Hsueh Hsieh

Szu-Yao Yu

Li-Wei Feng

Chan-Lon Yang

Ying-Chiao Wang

Che-Hua Hsu

Zhi-Cheng Lee

Yi-Wen Chen

Kai-Jiun Chang

Yi-An Huang

Chia-Chen Wu

Chia Chang Hsu

Min-Hsien Chen

Shu-Min Huang

Chung-Yen Feng

Hui-Ting Lin

Jing-Gang Li

Jian-Hong Su

Teng-Chun Tsai

Chien-Ting Lin

Ching-Wen Hung

Chun-Hsien Lin

Chih-Sen Huang

Chia-Lin Hsu

Yi-Hui Lee

Jia-Rong Wu

Tzyy-Ming Cheng

Chien-Ming Lai

Ching-Ling Lin

Po-Cheng Huang

Cheng-Guo Chen

Po-Jui Liao

Jie-Ning Yang

Tong-Jyun Huang

Chun-Ling Lin

Shao-Hua Hsu

Tsung-Hung Chang

Guang-Yaw Hwang

Tsung-Lung Tsai

Ko-Wei Lin

Hung-Ling Shih

Jung-Tsung Tseng

A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a contact hole in the first IMD layer; forming a bottom electrode layer in the contact hole; forming a magnetic tunneling junction (MTJ) stack on the bottom electrode layer; and removing the MTJ stack and the bottom electrode layer to form a MTJ on a bottom electrode. Preferably, the bottom electrode protrudes above a top surface of the first IMD layer.

Semiconductor device and method for fabricating the same

A high electron mobility transistor (HEMT) includes a substrate, a channel layer, a barrier layer and a passivation layer. A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a metal layer, and the metal layer includes a metal material doped with a first additive. A weight percentage of the first additive in the metal layer is between 0% and 2%.

High electron mobility transistor and method for forming the same

A method for forming a thin film resistor with improved thermal stability is disclosed. A substrate having thereon a first dielectric layer is provided. A resistive material layer is deposited on the first dielectric layer. A capping layer is deposited on the resistive material layer. The resistive material layer is then subjected to a thermal treatment at a pre-selected temperature higher than 350 degrees Celsius in a hydrogen or deuterium atmosphere. The capping layer and the resistive material layer are patterned to form a thin film resistor on the first dielectric layer.

Method for forming a thin film resistor with improved thermal stability

The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).

Storage node contact structure of a memory device

An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.

ReRAM structure and method of fabricating the same

A method of manufacturing a semiconductor device for preventing row hammering issue in DRAM cell, including the steps of providing a substrate, forming a trench in the substrate, forming a gate dielectric conformally on the trench, forming an n-type work function metal layer conformally on the substrate and the gate dielectric, forming a titanium nitride layer conformally on the n-type work function metal layer, and filling a buried word line in the trench.

Semiconductor structure for preventing row hammering issue in DRAM cell and method for manufacturing the same

Storage node contact structure of a memory device and manufacturing methods thereof

A semiconductor structure for preventing row hammering issue in DRAM cell is provided in the present invention. The structure includes a trench with a gate dielectric, an n-type work function metal layer, a TiN layer conformally formed within, and a buried word line filled in the trench.

A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. The low resistive layer includes a carbonitride of a first metal material, and the first metal bulk includes the first metal material.

Conductive structure and method for manufacturing conductive structure

A manufacturing method of a metal gate structure includes the following steps. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. The silicon-containing work function layer includes a vertical portion and a horizontal portion. Finally, the gate trench is filled up with a conductive metal layer.

Manufacturing method of metal gate structure

A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided.

Semiconductor process for forming plug

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Tainan, Taiwan

Hsin-Fu Huang