Taiwan Semiconductor Manufacturing Comp. Ltd.

Hsin-Chang Lee

Ta-Cheng Lien

Pei-Cheng Hsu

Chia-Jen Chen

Anthony Yen

Yun-Yue Lin

Chih-Cheng Lin

Ping-Hsun Lin

Chien-Cheng Chen

Ming-Wei Chen

Chin-Hsiang Lin

Wen-Chang Hsueh

Jong-Yuh Chang

Tzu Yi Wang

Jeng-Horng Chen

Chih-Tsung Shih

Tran-Hui Shen

Hung-Yi Tsai

Huan-Ling Lee

Shinn-Sheng Yu

Chih-Chiang Tu

Hao-Ping Cheng

Chun-Fu Yang

Shih-Ming Chang

Ting-Hao Hsu

Kuan-Wen Lin

Chue San Yoo

Ching-Huang Chen

Yih-Chen Su

Chen-Yang Lin

Yen-Cheng Ho

Chen-Shao Hsu

Da-Wei Yu

ShinAn Ku

Sheng-Chi Chin

Chi-Lun Lu

Wei-Che Hsieh

Hsuan-Chen Chen

Tao-Min Huang

Burn Jeng Lin

Hung-Chang Hsieh

Hua-Tai Lin

Chun-Lang Chen

Tsiao-Chen Wu

Chang-Cheng Hung

Li-Hsin Wang

Chung-Hsuan Liu

Ming-Jiun Yao

Lee-Chih Yeh

Ku-Hsiang Sung

Szu-Ping Tsai

Shih-Jui Huang

Gaston Lee

Amo Chen

Tsai-Sheng Gau

Yen-Cheng Lu

Yao-Ching Ku

Wei-Jen Lo

Ching-Fang Yu

Kun-Lung Hsieh

Hung Chang Hsieh

Ren-Guey Hsieh

Chih-cheng Chen

Chi-Yuan Sun

Tzu-Yi Wang

Wei-Hao Lee

Hong-Chang Hsieh

Ken Wu

Luke Hsu

Mark Chien

Hsuan-I Wang

Wei-Shiuan Chen

Yeh Lee-Chih

Wen-Yao Wei

Chi-Kuang Tsai

Yi-Fu Hsieh

Chia-Shiung Tsai

Li-Jui Chen

Chih-Wei Hsu

Ping-Yin Liu

Wen-Chun Huang

Wen-Chuan Wang

Kuei Shun Chen

Cheng-Cheng Kuo

Shu-Hao Chang

Shih-Che Wang

Chih-Shiang Chou

Fu-Sheng Chu

Tzu-Chun Lo

Ching-Che Tsai

Yen-Bin Huang

Chen-Yuan Hsia

Chia-Tung Kuo

Amö Chen

Chia-Tsung Shih

Pei-Chung Hsu

Chi-Ping Wen

Kai-Chung Liu

Chih-Tao Chien

Ting-Pi Sun

An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a multi-layer patterned absorber layer on the reflective multilayer stack is provided. Disclosed embodiments include an absorber layer that includes an alloy comprising ruthenium (Ru), chromium (Cr), platinum (Pt), gold (Au), iridium (Ir), titanium (Ti), niobium (Nb), rhodium (Rh), molybdenum (Mo), tungsten (W) or palladium (Pd), and at least one alloying element. The at least one alloying element includes ruthenium (Ru), chromium (Cr), tantalum (Ta), platinum (Pt), gold (Au), iridium (Ir), titanium (Ti), niobium (Nb), rhodium (Rh), molybdenum (Mo), hafnium (Hf), boron (B), nitrogen (N), silicon (Si), zirconium (Zr) or vanadium (V). Other embodiments include a multi-layer patterned absorber structure with layers that include an alloy and an alloying element, where at least two of the layers of the multi-layer structure have different compositions.

Extreme ultraviolet mask with alloy based absorbers

A pellicle assembly includes a pellicle membrane with a nanotube layer formed from nanotubes having a minimum length of 1,000 μm. The pellicle membrane can be formed with multiple layers and has a combination of high transmittance, low deflection, and small pore size. A conformal coating may applied to an outer surface of the pellicle membrane. The conformal coating is intended to protect the pellicle membrane from damage that can occur due to heat and hydrogen plasma created during EUV exposure.

Methods to improve mechanical properties of pellicle membrane

In a method of de-mounting a pellicle from a photo mask, the photo mask with the pellicle is placed on a pellicle holder. The pellicle is attached to the photo mask by a plurality of micro structures. The plurality of micro structures are detached from the photo mask by applying a force or energy to the plurality of micro structures before or without applying a pulling force to separate the pellicle from the photo mask. The pellicle is de-mounted from the photo mask. In one or more of the foregoing and following embodiments, the plurality of micro structures are made of an elastomer.

EUV pellicle and mounting method thereof on photo mask

A mask container for storing a mask for photolithography, includes a cover and a base having a plurality of tapered corners. The tapered corners taper outward and downward from a top major surface of the base. The cover having the tapered corners extends downward that covers the tapered corners of the base when the cover is attached to the base. The tapered corners of the cover are tapered at about the same angle as the tapered corners of the base so that a surface of the tapered corners of the cover is substantially parallel to a corresponding surface of the tapered corner of the base when the cover is attached to the base. A recess is located in the tapered corners of the cover. A biasing member and a ball-shaped member are located in the tapered corners of the base to mate with the recess when the cover is attached to the base.

Reticle container

Coated nanotubes and bundles of nanotubes are formed into membranes useful in optical assemblies in EUV photolithography systems. These optical assemblies are useful in methods for patterning materials on a semiconductor substrate. Such methods involve generating, in a UV lithography system, UV radiation. The UV radiation is passed through a coating layer of the optical assembly, e.g., a pellicle assembly. The UV radiation that has passed through the coating layer is passed through a matrix of individual nanotubes or matrix of nanotube bundles. UV radiation that passes through the matrix of individual nanotubes or matrix of nanotube bundles is reflected from a mask and received at a semiconductor substrate.

Optical assembly with coating and methods of use

A pellicle assembly includes a pellicle membrane with a nanotube layer formed from thick nanotube bundles. The pellicle membrane can be formed with multiple layers and has a combination of long lifetime, high transmittance, low deflection, and small pore size. A conformal coating may applied to an outer surface of the pellicle membrane. The conformal coating protects the pellicle membrane from damage that can occur due to heat and hydrogen plasma created during EUV exposure.

Pellicle membrane with improved properties

In a method of manufacturing a reflective mask, a photo resist layer is formed over a mask blank. The mask blank includes a substrate, a reflective multilayer on the substrate, a capping layer on the reflective multilayer, an absorber layer on the capping layer and a hard mask layer, and the absorber layer is made of Cr, CrO or CrON. The photo resist layer is patterned, the hard mask layer is patterned by using the patterned photo resist layer, the absorber layer is patterned by using the patterned hard mask layer, and an additional element is introduced into the patterned absorber layer to form a converted absorber layer.

EUV photo masks and manufacturing method thereof

Methods for plasma stability in a plasma treatment tool are disclosed. A laser is positioned within a plasma treatment chamber within a skin depth of the electromagnetic field generated therein. The laser can be synchronized with the electrical triggering signals that generate the electromagnetic field. This scheme provides a stable and efficient method of plasma ignition.

Methods and systems for improving plasma ignition stability

A method of inspecting an outer surface of a mask pod includes moving a stage holding a mask pod such that the stage stops at each location of a plurality of locations under an outer surface of the mask pod for a predefined amount of time. At each location of the plurality of locations, the method further includes directing a stream of air to the outer surface of the mask pod, capturing an image of scattered air from each location of the plurality of locations of the outer surface of the mask pod, and determining a number of particles in the scattered air as a sampled number of particles based on the captured image. The method also includes generating a map of particles on the outer surface of the mask pod based on the sampled number of particles at each of the plurality of locations.

High throughput and high position accurate method for particle inspection of mask pods

In a method of manufacturing a semiconductor device a semiconductor wafer is retrieved from a load port. The semiconductor wafer is transferred to a treatment device. In the treatment device, the surface of the semiconductor wafer is exposed to a directional stream of plasma wind to clean a particle from the surface of the semiconductor wafer. The stream of plasma wind is generated by an ambient plasma generator and is directed at an oblique angle with respect to a perpendicular plane to the surface of the semiconductor wafer for a predetermined plasma exposure time. After the cleaning, a photo resist layer is disposed on the semiconductor wafer.

Method and device for cleaning substrates

A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes a base material made of one or more of a Cr based material, an Ir based material, a Pt based material, or Co based material, and further contains one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.

A lithography mask including a substrate, a phase shift layer on the substrate and an etch stop layer is provided. The phase shift layer is patterned and the substrate is protected from etching by the etch stop layer. The etch stop layer can be a material that is semi-transmissive to light used in photolithography processes or it can be transmissive to light used in photolithography processes.

Lithography mask and methods

A reflective mask includes a substrate, a lower reflective multilayer disposed over the substrate, an intermediate layer disposed over the lower reflective multilayer, an upper reflective multilayer disposed over the intermediate layer, a capping layer disposed over the upper reflective multilayer, and an absorber layer disposed in a trench formed in the upper reflective layers and over the intermediate layer. The intermediate layer includes a metal other than Cr, Ru, Si, Si compound and carbon.

A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes one or more alternating pairs of a first Cr based layer and a second Cr based layer different from the first Cr based layer.

Methods of making a semiconductor device

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Zhubei, Taiwan

Hsin-Chang Lee