Taiwan Semiconductor Manufacturing Comp. Ltd.

Hsien-Pin Hu

Shang-Yun Hou

Chen-Hua Douglas Yu

Shin-Puu Jeng

Wen-Hsin Wei

Wei-Cheng Wu

Chi-Hsi Wu

Tzuan-Horng Liu

Hsiao-Tsung Yen

Jing-Cheng Lin

Ying-Ching Shih

Tzu-Yu Wang

Ming-Fa Chen

Wen-Chih Chiou

Wei-Ming Chen

Shih-Wen Huang

Chung-Yu Lu

Szu-Wei Lu

Chin-Wei Kuo

Chao-Hsiang Yang

Tsung-Shu Lin

Tsung-Yu Chen

Tzu-Wei Chiu

Wen Hsin Wei

Kuo-Ching Hsu

Cheng-Hsien Hsieh

Sally Liu

Weiming Chris Chen

Yung-Chi Lin

Wensen Hung

Chin-Fu Kao

Chun Hua Chang

Jhe-Ching Lu

Chi-Chun Hsieh

Jiun Ren Lai

Hsing-Kuo Hsia

Sung-Hui Huang

Kuan-Yu Huang

Li-Chung Kuo

Hung-Jung Tu

Heh-Chang Huang

Chen-Hsiang Lao

Yushun Lin

Chih-Chieh Hung

An-Jhih Su

Yu-Ling Lin

Min-Chie Jeng

Kim Hong Chen

Sao-Ling Chiu

Liang-Chen Lin

Ping-Kang Huang

Shih-Kai Lin

Shih-Cheng Chang

Jyun-Lin Wu

Chih-Ching Lin

Tsung-Yang Hsieh

Chun-Che Chen

Chih-Kai Cheng

Jung Cheng Ko

Fu-Tsai Hou

Tung-Chin Yeh

Gia-Her Lu

Chih-Ta Shen

Jhih-Ming Lin

Wen-Jung Chuang

Li-Hui Cheng

Shou-Zen Chang

Kuo-Chiang Ting

Li-Han Hsu

Chih-Chien Pan

Hsuan-Ning Shih

Chun-Yi Liu

Meng-Han Lee

Chia-Nan Lee

An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Integrated circuit package and method of forming same

A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

Method for forming a semiconductor device including forming a first interconnect structure on one side of a substrate having first metal feature closer the substrate than second metal feature and forming first and second tsv on other side of substrate connecting to the metal features

Semiconductor devices and methods of manufacture are provided. In embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.

Semiconductor devices and methods of manufacture

A method includes performing a first light-exposure and a second a second light-exposure on a photo resist. The first light-exposure is performed using a first lithograph mask, which covers a first portion of the photo resist. The first portion of the photo resist has a first strip portion exposed in the first light-exposure. The second light-exposure is performed using a second lithograph mask, which covers a second portion of the photo resist. The second portion of the photo resist has a second strip portion exposed in the second light-exposure. The first strip portion and the second strip portion have an overlapping portion that is double exposed. The method further includes developing the photo resist to remove the first strip portion and the second strip portion, etching a dielectric layer underlying the photo resist to form a trench, and filling the trench with a conductive feature.

Forming large chips through stitching

A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a cap and outer flanges. The cap overlies the semiconductor package. The outer flanges are disposed at edges of the cap, are connected with the cap, and extend towards the circuit substrate. A region of the bottom surface of the cap has a curved profile matching a warpage profile of the semiconductor package and the circuit substrate, and the region having the curved profile extends over the semiconductor package.

Semiconductor device having heat dissipation structure of curved profile and a manufacturing method thereof

An apparatus for manufacturing packaged semiconductor devices includes a lower plate having package platforms and clamp guide pins to align an upper plate with the lower plate, and a boat tray having windows configured to receive package devices, and a plurality of upper plates configured to be aligned to respective windows and respective package platforms. Clamping force can be applied by fasteners configured to generate a downward force upon the upper plate. Package devices on the platforms are thus subjected to a clamping force. Load cells measure the clamping force so adjustments can be made.

Package structure and method and equipment for forming the same

Embodiments include packages and methods for forming packages which include interposers having a substrate made of a dielectric material. The interposers may also include a redistribution structure over the substrate which includes metallization patterns which are stitched together in a patterning process which includes multiple lateral overlapping patterning exposures.

Chiplet interposer

A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

Giga interposer integration through Chip-On-Wafer-On-Substrate

A package structure and method for forming the same are provided. The package structure includes a first through via structure formed in a substrate and a semiconductor die formed below the first through via structure. The package structure further includes a conductive structure formed in a passivation layer over the substrate. The conductive structure includes a first via portion and a second via portion, the first via portion is directly over the first through via structure, and there is no conductive material directly below and in direct contact with the second via portion.

Package structure including through via structures

Method for forming a semiconductor device having TSV formed through a silicon interposer and a second silicon substrate with cavity covering a second die

Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.

3D packages and methods for forming the same

A packaged semiconductor device and a method and apparatus for forming the same are disclosed. In an embodiment, a method includes bonding a device die to a first surface of a substrate; depositing an adhesive on the first surface of the substrate; depositing a thermal interface material on a surface of the device die opposite the substrate; placing a lid over the device die and the substrate, the lid contacting the adhesive and the thermal interface material; applying a clamping force to the lid and the substrate; and while applying the clamping force, curing the adhesive and the thermal interface material.

Giga interposer integration through chip-on-wafer-on-substrate

Growing community of inventors

Zhubei, Taiwan

Hsien-Pin Hu