Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

United Silicon Incorporated

Hsien-Liang Meng

Ming-Che Ho

Chung-Shi Liu

Hung-Jui Kuo

Mirng-Ji Lii

Wei-Hung Lin

Shih-Ming Lan

Chun-Liang Liu

Han-Ping Pu

Chun-Hung Lin

Yu-Feng Chen

Yi-Wen Wu

Yu-min Liang

Hung-Lin Shih

Chung-Chih Chen

Ying-Shin Han

Yen-Miao Lin

Hsun-Ying Huang

Chih-Hao Lin

Fu-Jen Li

Chen-Hua Tsai

Ren-Dou Lee

Wei-Tsun Shiau

Po-Lun Cheng

Chien-Kuo Chang

Wei-Chih Weng

Chih-Ho Tai

Bo-Chang Su

Che-Hung Liu

Chun-An Lin

Jimmy Liang

Huan-Shun Lin

Chia-Liang Chueh

Jih-Shun Chiang

Kuo-Chou Chen

Li-Yuen Tang

Ming-Chi Fan

Andrew Lin

Ho-Sung Liao

Chun-Wei Lin

Pu-Sheng Lee

A packaging structure and a method of forming a packaging structure are provided. The packaging structure, such as an interposer, is formed by optionally bonding two carrier substrates together and simultaneously processing two carrier substrates. The processing includes forming a sacrificial layer over the carrier substrates. Openings are formed in the sacrificial layers and pillars are formed in the openings. Substrates are attached to the sacrificial layer. Redistribution lines may be formed on an opposing side of the substrates and vias may be formed to provide electrical contacts to the pillars. A debond process may be performed to separate the carrier substrates. Integrated circuit dies may be attached to one side of the redistribution lines and the sacrificial layer is removed.

Package structures and methods for forming the same

A package includes a die on a surface of a package component. The package also includes a first die stack on the surface of the package component. The package further includes a first thermal interface material (TIM) having a first thermal conductivity and disposed on the first die stack. In addition, the package includes a second thermal interface material (TIM) having a second thermal conductivity and disposed on the die. The first thermal conductivity of the first TIM is different from the second thermal conductivity of the second TIM.

Packages with multi-thermal interface materials and methods of fabricating the same

A method of forming a semiconductor package includes dispensing an adhesive on a substrate that has an integrated circuit die attached thereon, placing a lid over the integrated circuit die such that a bottom surface of the lid caps at least a portion of the adhesive, and pressing the lid against the substrate such that a portion of the adhesive is squeezed from a space between the bottom surface of the lid and the substrate onto a sidewall of the lid.

Method of forming a semiconductor package

A semiconductor package includes a substrate, an integrated circuit die, a lid and an adhesive. The integrated circuit die is disposed over the substrate. The lid is disposed over the substrate. The lid includes a cap portion and a foot portion extending from a bottom surface of the cap portion. The cap portion and the foot portion define a recess, and the integrated circuit die is accommodated in the recess. The adhesive includes a sidewall portion and a bottom portion. The sidewall portion contacts a sidewall of the foot portion. The bottom portion extends from the sidewall portion to between a bottom surface of the foot portion and the substrate.

Semiconductor package and method of forming the same

A system and method for a zero stand-off configuration are provided. An embodiment comprises forming a seal layer over a conductive region that is part of a first substrate and breaching the seal with a conductive member of a second substrate in order to bond the first substrate to the second substrate.

Zero stand-off bonding system and method

Embodiments of mechanisms of a backside illuminated image sensor device structure are provided. The backside illuminated image sensor device structure includes a substrate having a frontside and a backside and a pixel array formed in the frontside of the substrate. The backside illuminated image sensor device structure further includes an antireflective layer formed over the backside of the substrate, and the antireflective layer is made of silicon carbide nitride.

Mechanisms for forming backside illuminated image sensor device structure

A sputtering target is provided that includes a planar backing plate and a target material formed over the planar backing plate and including an uneven sputtering surface including thick portions and thin portions and configured in conjunction with a sputtering apparatus such as a magnetron sputtering tool with a fixed magnet arrangement. The uneven surface is designed in conjunction with the magnetic fields that will be produced by the magnet arrangement such that the thicker target portions are positioned at locations where target erosion occurs at a high rate. Also provided is the magnetron sputtering system and a method for utilizing the target with uneven sputtering surface such that the thickness across the target to become more uniform in time as the target is used.

Sputtering target with reverse erosion profile surface and sputtering system and method using the same

A complementary metal-oxide-semiconductor (CMOS) device includes a substrate with a first active region and a second active region; a first gate structure and a second gate structure, respectively disposed on the first active region and the second active region; a first spacer structure and a second spacer structure respectively disposed on sidewalls of the first gate structure and the second gate structure; a first LDD and a second LDD respectively disposed in the substrate at both sides of the first gate structure and the second gate structure; an epitaxial material layer, disposed in the first active region and located on a side of the first LDD; and a passivation layer, disposed on the first gate structure, the first spacer structure, and the first LDD and covering the second active region, wherein the passivation layer comprises a carbon-containing oxynitride layer.

Complementary metal-oxide-semiconductor device and fabricating method thereof

A metal-oxide-semiconductor (MOS) transistor device is provided. The MOS transistor device includes a substrate, a gate structure, a spacer, a source/drain region and a barrier layer. The gate structure is disposed on the substrate. The gate structure includes a gate and a gate dielectric layer disposed between the gate and the substrate. The spacer is disposed on the sidewall of the gate structure. The source/drain region is disposed in the substrate on two sides of the spacer. The barrier layer is disposed around the source/drain region. The source/drain region and the barrier layer are fabricated using an identical material. However, the doping concentration of the source/drain region is larger than the doping concentration of the barrier layer.

Metal oxide semiconductor transistor device

A method of fabricating a shallow trench isolation structure is described. A mask layer is formed on a substrate. The mask layer and the substrate are patterned to form a trench in the substrate. A first deposition step and a second deposition step are performed to form a first isolation layer over the substrate. A third deposition step is performed to form a second isolation layer on the first isolation layer. The second isolation layer has a greater fluidity than the first isolation layer has. A planarization process is performed with the mask layer serving as a stop layer. A portion of the first isolation layer and the mask layer are removed to form the shallow trench isolation structure.

Method of fabricating shallow trench isolation structure

A method for manufacturing a shallow trench isolation. A substrate is provided, wherein the substrate has a pad oxide on the substrate and a silicon nitride layer on the pad oxide layer, and a trench penetrates through the silicon oxide layer and the pad oxide layer and into the substrate. A first oxide layer is conformally formed on the silicon nitride layer and in the trench. A rapid thermal process is performed. A second oxide layer is formed on the oxide layer to fill the trench. Portions of the first and the second oxide layers are removed to expose the silicon nitride layer.

Method of manufacturing shallow trench isolation

A method for forming an insulating layer to solve a problem of non-uniform thickness of the insulating layer is provided. The method includes forming a first insulating layer over a substrate preferably by chemical vapor deposition (CVD) at an operation temperature of about 200&deg; C.-350&deg; C. The thickness of the first insulating layer is about 500 &angst;-5000 &angst;. A second insulating layer is formed over the first insulating layer preferably by CVD at a temperature of about 350&deg; C.-500&deg; C. The thickness of the second insulating layer is about 1000 &angst;-10000 &angst;. The first and the second insulating layers form together as an insulating layer to insulate transistors and isolation structures from the interconnect metal layer.

Method for forming an insulating film

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Hsinchu, Taiwan

Hsien-Liang Meng