Globalfoundries Inc.

Globalfoundries U.S. Inc.

Hsien-Ching Lo

Yi Qi

Hui Zang

Jianwei Peng

Wei Hong

Yanping Shen

Yongjun Shi

Ruilong Xie

Zhenyu Hu

Xusheng Kevin Wu

Jerome Ciavatti

Haiting Wang

Tao Han

Jae Gon Lee

Hui Zhan

Alina Vinslava

Judson Robert Holt

Hong Yu

Jinping Liu

Sipeng Gu

Liu Jiang

Kangguo Cheng

Tenko Yamashita

Chanro Park

Julien Frougier

Lars W Liebmann

Min Gyu Sung

Xunyuan Zhang

Laertis Economikos

Daniel Chanemougame

Shesh Mani Pandey

Chun-Chen Yeh

Joseph Francis Shepard, Jr

Kwan-Yong Lim

Lei Sun

Randy W Mann

Bingwu Liu

Guowei Xu

Zhao Lun

Chun Yu Wong

Qun Gao

Xing Zhang

Manoj Joshi

Byoung-Gi Min

Wen Zhi Gao

Pei Zhao

Zhaoying Hu

Dongil Choi

Yong Jun Shi

Jianghu Yan

Edward Reis

Sang Woo Lim

Emilie M S Bourjot

Yoong Hooi Yong

Joo Tat Ong

James Psillas

Yongiun Shi

Kyung-Bum Koo

Basab Banerjee

The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion break device and methods of manufacture. The structure includes a single diffusion break structure with a fill material between sidewall spacers of the single diffusion break structure and a channel oxidation below the fill material.

Single diffusion break device for FDSOI

Structures for a field-effect transistor and methods for fabricating a structure for a field-effect transistor. First and second device structure are respectively formed in first and second device regions, and a first dielectric layer is formed over the first and second device regions. The first dielectric layer includes a recess defining a step at a transition between the first and second device regions, and a second dielectric layer is arranged within the recess in the first dielectric layer. A third dielectric layer is arranged over the first dielectric layer in the first device region and over the second dielectric layer in the second device region. A contact, which is coupled with the second device structure, extends through the first, second, and third dielectric layers in the second device region.

Etch stop layer for use in forming contacts that extend to multiple depths

One illustrative FinFET device disclosed herein includes a source/drain structure that, when viewed in a cross-section taken through the fin in a direction corresponding to the gate width (GW) direction of the device, comprises a perimeter and a bottom surface. The source/drain structure also has an axial length that extends in a direction corresponding to the gate length (GL) direction of the device. The device also includes a metal silicide material positioned on at least a portion of the perimeter of the source/drain structure for at least a portion of the axial length of the source/drain structure and on at least a portion of the bottom surface of the source/drain structure for at least a portion of the axial length of the source/drain structure.

FinFET device with a wrap-around silicide source/drain contact structure

Methods form structures that include (among other components) semiconductor fins extending from a substrate, gate insulators contacting channel regions of the semiconductor fins, and gate conductors positioned adjacent the channel regions and contacting the gate insulators. Additionally, epitaxial source/drain material contacts the semiconductor fins on opposite sides of the channel regions, and source/drain conductive contacts contact the epitaxial source/drain material. Also, first insulating spacers are on the gate conductors. The gate conductors are linear conductors perpendicular to the semiconductor fins, and the first insulating spacers are on both sides of the gate conductors. Further, second insulating spacers are on the first insulating spacers; however, the second insulating spacers are only on the first insulating spacers in locations between where the gate conductors intersect the semiconductor fins.

Fin-type transistors with spacers on the gates

Described herein are nanosheet-FET structures having a wrap-all-around contact where the contact wraps entirely around the S/D epitaxy structure, thereby increasing contact area and ultimately allowing for improved S/D contact resistance. Other aspects described include nanosheet-FET structures having an air gap as a bottom isolation area to reduce parasitic S/D leakage to the substrate.

Wrap-all-around contact for nanosheet-FET and method of forming same

Methods form devices by patterning a lower layer to form a fin, and forming a sacrificial gate along sidewalls of the fin. Such methods form a mask with cut openings on the sacrificial gate and remove sections of the fin and the sacrificial gate exposed through the cut openings to divide the fin into fin portions and create cut areas between the fin portions. Additionally, these methods remove the mask, epitaxially grow source/drains in the cut areas, replace the sacrificial gate with a gate conductor, and form a gate contact on the gate conductor over a center of the fin portions.

FinFETs having gates parallel to fins

Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A first dielectric layer is deposited over a first gate structure in a first device area and a second gate structure in a second device area, and then planarized. A second dielectric layer is deposited over the planarized first dielectric layer, and then removed from the first device area. After removing the second dielectric layer from the first device area, the first dielectric layer in the first device area is recessed to expose the first gate structure. A silicide is formed on the exposed first gate structure.

Field-effect transistors with improved dielectric gap fill

A semiconductor structure including a source/drain region is disclosed. The source/drain region may include a first epitaxial region along at least one sidewall of the source/drain region having a substantially uniform sidewall thickness. The semiconductor structure may further include a gate structure adjacent and above the source/drain region wherein at least a portion of the first epitaxial region is positioned below a sidewall spacer of the gate structure. A method of forming a source/drain region including a first epitaxial region having a substantially uniform sidewall thickness is disclosed. The method may include forming a trench in a substrate adjacent to a gate structure, forming the first epitaxial region in the trench, forming a spacer material layer on the gate structure and on a portion of the first epitaxial region, and removing a portion of the first epitaxial region using the spacer material layer as a mask.

Epitaxial region for embedded source/drain region having uniform thickness

Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. A first spacer is located adjacent to a vertical sidewall of a gate electrode, a second spacer located between the first spacer and the vertical sidewall of the gate electrode, and a third spacer located between the second spacer and the vertical sidewall of the gate electrode. The first spacer has a higher dielectric constant than the second spacer. The first spacer has a higher dielectric constant than the third spacer. The third spacer has a lower dielectric constant than the second spacer.

Multiple-layer spacers for field-effect transistors

A method of manufacturing a vertical fin field effect transistor includes forming a first fin in a first device region of a substrate, forming a second fin in a second device region of the substrate, and forming a sacrificial gate having a first gate length adjacent to the first and second fins. After forming a block mask over the sacrificial gate within the first device region, a deposition step or an etching step is used to increase or decrease the gate length of the sacrificial gate within the second device region. Top source/drain junctions formed over the fins are self-aligned to the gate in each of the first and second device regions.

Multiple gate length device with self-aligned top junction

The disclosure provides integrated circuit (IC) structures with single diffusion break (SDB) abutting end isolation regions, and methods of forming the same. An IC structure may include: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on the plurality of fins and laterally between the plurality of gate structures; at least one single diffusion break (SDB) positioned within the insulator region and one of the plurality of fins, the at least one SDB region extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region abutting a lateral end of the at least one SDB along a length of the plurality of gate structures, the end isolation region extending substantially in parallel with the plurality of fins.

Intergrated circuit structure including single diffusion break abutting end isolation region, and methods of forming same

Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.

Single-curvature cavity for semiconductor epitaxy

Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.

Dual-curvature cavity for epitaxial semiconductor growth

Disclosed are embodiments of an improved method for forming a vertical field effect transistor (VFET). In each of the embodiments of the method, a semiconductor fin is formed sufficiently thick (i.e., wide) so that the surface area of the top of the semiconductor fin is sufficiently large to facilitate epitaxial growth thereon of a semiconductor material for a second source/drain region. As a result, the second source/drain region will be sufficiently large to avoid potential contact-related defects (e.g., unlanded contacts, complete silicidation of second source/drain region during contact formation, etc.). Additionally, either before or after this second source/drain region is formed, at least the center portion of the semiconductor fin, which will include the channel region of the VFET, is thinned down to a desired critical dimension for optimal VFET performance. Also disclosed are VFET structure embodiments resulting from this method.

Method of forming a vertical field effect transistor (VFET) and a VFET structure

The present disclosure relates to semiconductor structures and, more particularly, to an N-P boundary spacer structure used with finFET devices and methods of manufacture. The method includes forming a plurality of first fin structures, forming a blocking layer between a first fin structure of the plurality of fin structures and a second fin structure of the plurality of fin structures, and forming an epitaxial material on the first fin structure, while blocking the epitaxial material from extending onto the second fin structure by at least the blocking layer formed between the first fin structure and the second fin structure.

Boundary spacer structure and integration

Growing community of inventors

Clifton Park, NY, United States of America

Hsien-Ching Lo