International Business Machines Corporation

Hsichang Liu

Harry David Cox

Krystyna Waleria Semkow

Renee L Weisman

Charles Leon Arvin

Govindarajan Natarajan

Jeffrey A Brody

Mark J LaPlante

Brian Richard Sundlof

John Joseph Garant

Gregg B Monjeau

Jay A Bunt

Donald W Diangelo

Paul G McLaughlin

Thomas A Kline

Cristian Docu

Thomas Foley

Melvin R Gottschalk, Jr

Lisa A Hamilton

Sebastian Loscerbo

Olga A Otieno

Gareth Geoffrey Hougham

Eric D Perfecto

Shaji Farooq

Kamalesh K Srivastava

Peter Jeffrey Brofman

Donald W Henderson

Suryanarayana Kaja

Julien Sylvestre

Srinivasa S N Reddy

Karen P McLaughlin

Kim H Ruffing

Alexandre Blander

Nike Oluwakemi Medahunsi

Tom Wayson

Louis L Hsu

Lawrence Shungwei Mok

Hilton T Toy

Kamal Kumar Sikka

Louis C Hsu

Sushumna Iruvanti

James N Humenik

Howard Hao Chen

Mark William Kapfhammer

Dinesh Gupta

Daniel George Berger

Arthur Gilman Merryman

Jiantao Zheng

Richard D Langlois

Wei Zou

John A Trumpetto

Hai Pham Longworth

James R Salimeno, Iii

Charles Timothy Ryan

Ahmed Sayeed Shah

Carla A Bailey

Gerard John Nuzback

Hua Gan

Vall F McClean

Srinivasa Sn Reddy

James C Monaco

Evelyn Barrington

Lorraine Di Piero-Simmonds

Edward J Hassdenteufel, Iii

Richard C Steger

In one embodiment of the present invention, inert nano-sized particles having dimensions from 1 nm to 1,000 nm are added into a solder ball. The inert nano-sized particles may comprise metal oxides, metal nitrides, metal carbides, metal borides, etc. The inert nano-sized particles may be a single compound, or may be a metallic material having a coating of a different material. In another embodiment of the present invention, a small quantity of at least one elemental metal that forms stable high melting intermetallic compound with tin is added to a solder ball. The added at least one elemental metal forms precipitates of intermetallic compounds with tin, which are dispersed as fine particles in the solder.

Additives for grain fragmentation in Pb-free Sn-based solder

A frontside of a chip is bonded to a top surface of a chip carrier. Seal material is dispensed at a periphery of the top surface of the chip carrier. A solder TIM having a first side and a second side is provided. The first side of the TIM contacts a backside of the chip. A reflow is performed to melt the TIM. The second side of the TIM is bonded to a lid. The seal material is cured. The lid is attached to the top surface of the chip carrier. Backfill material is injected into a space between the top surface of the chip carrier and the lid. The backfill material abuts sides of the TIM. The backfill material is cured. TIM solder cracking and associated thermal degradation are mitigated.

Reliability enhancement of metal thermal interface

An apparatus for providing uniform axial load distribution for laminate layers of multilayer ceramic chip carriers includes a base plate configured to support a plurality of green sheet layers thereon, the base plate having at least one resiliently mounted load support bar disposed adjacent outer edges of the base plate. The load support bar is mounted on one or more biasing members such that the top surface of the support bar extends above the top surface of the base plate by a selected distance.

Apparatus for providing uniaxial load distribution for laminate layers of multilayer ceramic chip carriers

Method for providing uniaxial load distribution for laminate layers of multilayer ceramic chip carriers

One embodiment of the present invention is directed to an under bump metallurgy material. The under bump metallurgy material of this embodiment includes an adhesion layer and a conduction layer formed on top of the adhesion layer. The under bump metallurgy material of this embodiment also includes a barrier layer plated on top of the conduction layer and a sacrificial layer plated on top of the barrier layer. The conduction layer of this embodiment includes a trench formed therein, the trench contacting a portion of the barrier layer and blocking a path of intermetallic formation between the conduction layer and the sacrificial layer.

Intermetallic diffusion block device and method of manufacture

A structure. The structure includes a layered configuration including a copper layer, a first layer, and a second layer. The first and second layers are disposed on opposite sides of the copper layer and are in direct mechanical contact with the copper layer. The first and second layers each include a same alloy of nickel and a metal consisting of cobalt, iron, copper, manganese, or molybdenum. A first region in the first layer extends completely through the first layer. A second region in the second layer extends completely through the second layer. A third region in the first layer extends completely through the first layer. The third region does not extend into any portion of the second layer. The first, second region, and third regions each include a photoresist or an opening such that photoresist or opening extends completely through the first, second, and first layer, respectively.

Nickel alloy plated structure

An apparatus for providing two-phase heat transfer for semiconductor devices includes a vapor chamber configured to carry a cooling liquid, the vapor chamber having base section, and a plurality of three-dimensional (3D) shaped members. The plurality of 3D-shaped members have interior and exterior sidewalls, the 3D-shaped members being connected to the base section so that vapor carrying latent heat can reach the respective interior sidewalls and get transferred to the respective exterior sidewalls configured to be in contact with an external coolant. The vapor chamber is configured to be in contact with a semiconductor device in order to remove heat therefrom.

Apparatuses for dissipating heat from semiconductor devices

An improved Land Grid Array interconnect structure is provided with the use of small metal bumps on the substrate electrical contact pad. The bumps interlock with segments of the fuzz button connection and increase the physical contact surface area between the contact pad and fuss button. The improved contact reduces displacement of electrical contact points due to thermo-mechanical stress and lowers the required actuation force during assembly.

Micro-bumps to enhance LGA interconnections

A structure and associated methods of formation. The structure includes a layered configuration comprising a copper layer, a first layer, and a second layer. The copper layer consists essentially of copper. The first and second layers are disposed on opposite sides of the copper layer and are in direct mechanical contact with the copper layer. The first and second layers each consist essentially of a same alloy of nickel and cobalt having a weight percent concentration of cobalt in a range of 3% to 21%. A through hole in the layered configuration extends completely through the first layer, the copper layer, and the second layer, wherein a first opening in the layered configuration extends completely through the first layer and does not extend into any portion of the second layer.

Disclosed is a method of manufacturing integrated circuit chips that partially joins an integrated circuit wafer to a supporting wafer at a limited number of joining points. Once joined, the integrated circuit wafer is chemically-mechanically polished to reduce the thickness of the integrated circuit wafer. Then, after reducing the thickness of the integrated circuit wafer, the invention performs conventional processing on the integrated circuit wafer to form devices and wiring in the integrated circuit wafer. Next, the invention cuts through the integrated circuit wafer and the supporting wafer to form chip sections. During this cutting process, the integrated circuit wafer separates from the supporting wafer in chip sections where the integrated circuit wafer is not joined to the supporting wafer by the joining points. Chip sections where the integrated circuit wafer remains joined to the supporting wafer are thicker than the chips sections where the integrated circuit wafer separates from the supporting wafer.

Partial wafer bonding and dicing

A method and apparatus are provided for reworking of finishing metallurgy on pads of electronic components. The pads are copper or copper/nickel and have a layer of nickel thereon and an overlying layer of gold. The gold layer is removed first followed by the nickel layer and then the component is treated to remove etch and corrosion products. Media blasting is then used to restore the pads to their original condition as on prime parts. The pads are then replated using conventional nickel and gold plating solutions to form the reworked component.

Rework method for finishing metallurgy on chip carriers

A screening mask having a stress-relieving area including an inner functional area having a pattern which is replicated on an underlying substrate, the inner functional area pattern having an one open area through which a paste is extruded and at least one tab, and an outer nonfunctional area distinct from the inner functional area, the outer nonfunctional area having a stress-relieving area adjacent to an edge of the screening mask that protects the at least one tab in the inner functional area from breaking.

Screening mask having a stress-relieving area

A method for minimizing formation of cracks at junctions between conductive vias and conductive lines in line-to-via connections on a substrate. The method comprises providing a transition zone connected between a base section of the line and a cap, the transition zone providing a volume of conductive paste during a conductive paste screen printing operation that is greater than the volume provided by the base section being directly connected to the cap. In particular, the transition zone volume is an effective amount to prevent necking of the conductive line into the via when the mask is misaligned to the substrate within an expected alignment tolerance. The transition zone may comprise a jogged end extending from the base section to the cap at an angle to the line, or a flared end extending from the base section. Line-to-via connection structures, patterns on a mask for making such structures, and masks having such patterns are also disclosed.

Method of forming conductive line features for enhanced reliability of multi-layer ceramic substrates

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Fishkill, NY, United States of America

Hsichang Liu