Vanguard International Semiconductor Corporation

Hsiao-Ying Yang

Shih-Ming Chen

Chih-Ping Lin

Pi-Kuang Chuang

Hung-Li Chang

Chih-Cherng Liao

Hsing-Chao Liu

Ya-Sheng Liu

Hung-Chih Tan

Shao-Chang Huang

Yeh-Ning Jou

Kai-Chieh Hsu

Chung-Ren Lao

Chien-Hsien Song

Li-Fan Chen

Chun-Chih Chen

Yeh-Sen Lin

Ching-Ho Li

Ting-You Lin

Po-Sheng Hu

Kai-Chuan Kan

Gong-Kai Lin

Chi-Hua Yu

Fu-Chun Tseng

Che-Hua Chang

Jing-Da Li

Shih-Ming Tseng

Kai-Chun Chen

Chien-Chi Hsu

Wei-Lun Hsia

Kuan-I Ho

Chun-Hsien Lin

Kuo-Chien Hsu

Wen-Hsien Liu

A semiconductor device includes a first metal layer, a second metal layer, and an inter-metal dielectric layer disposed between the first metal layer and the second metal layer. The inter-metal dielectric layer includes: a first dielectric layer disposed on the first metal layer and in direct contact with the first metal layer, wherein the first dielectric layer has a stress value less than 0; a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer has a stress value greater than 0; and a third dielectric layer disposed on the second dielectric layer, wherein the third dielectric layer has a stress value less than 0. A thickness of the third dielectric layer is greater than a thickness of the second dielectric layer, and the thickness of the second dielectric layer is greater than a thickness of the first dielectric layer.

Semiconductor device and method forming the same

A method for forming a semiconductor structure includes providing a substrate including a first region with a first gate structure and a second region with a second gate structure. First to third dielectric layers are formed on the substrate. The third dielectric layer is patterned to form a first portion in the first region and a second portion in the second region. The second region is covered and at least a portion of the first portion is removed to form a first mask. The second dielectric layer is pattern by using the first mask and the second portion as the second mask to expose a portion of the first dielectric layer. The portion of the first dielectric layer is removed to form a first stacked spacer on the first gate structure and a second stacked spacer on the second gate structure.

Semiconductor structure and method for forming the same

A high-voltage semiconductor device includes a substrate, a first insulating structure, a gate, a drain region, a source region and a doped region. The substrate has a first conductive type, and the first insulating structure is disposed on the substrate. The drain region and the source region are disposed in the substrate. The source region has a first portion and a second portion. The first portion has the second conductive type and the second portion has the first conductive type. The gate is disposed on the substrate, between the source region and the drain region to partially cover a side of the first insulating structure. The doped region is disposed in the substrate and has a first doped region and a second doped region, and the first doped region and the second doped region both include the first conductive type and separately disposed under the first insulating structure.

High-voltage semiconductor device

The present disclosure provides a high voltage semiconductor device includes a substrate, a first well region, a second well region, a source, a drain, a first electrode structure and a second electrode structure. The first well region and the second well region are disposed in the substrate, and which includes a first conductive type and a second conductive type which are complementary with each other. The source and the drain are respectively disposed within the first well region and the second well region. The first electrode structure and the second electrode structure are both disposed on the substrate, and the distance between the top surface of an electrode of the first electrode structure and the top surface of the substrate includes a first height and a second height which are different from each other.

High voltage semiconductor device

A semiconductor device includes a semiconductor substrate, a Schottky layer, a plurality of first doped regions, a plurality of second doped regions, a first conductive layer and a second conductive layer. The semiconductor substrate includes a first conductive type, and the Schottky layer is disposed on the semiconductor substrate. The first doped regions and the second doped regions include a second conductive type, and which are disposed within the semiconductor substrate. The first doped regions are in parallel and extended along a first direction, and the second doped regions are in parallel and extended along a second direction to cross the first doped regions, thereby to define a plurality of grid areas. The first conductive layer is disposed on the Schottky layer, and the second conductive layer is disposed under the semiconductor substrate.

Semiconductor device

A semiconductor structure includes a conductive feature on a substrate. A plurality of first dielectric layers are disposed on the conductive feature, and stress directions of at least two of the first dielectric layers are different from one another. A first hole penetrates through the plurality of the first dielectric layers to expose the conductive feature. A first conductive plug conformally covers the first hole and is electrically connected to the conductive feature. A first insulating plug on the first conductive plug fills the first hole.

Semiconductor structure and method for fabricating the same

A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.

Method for fabricating semiconductor device with increased breakdown voltage

A semiconductor device fabricating method is described. The semiconductor device fabricating method includes providing a substrate. A first gate insulating layer and a second gate insulating layer are formed on the substrate, respectively. A gate layer is blanketly formed. A portion of the gate layer, the first gate insulating layer and the second gate insulating layer are removed to form a first gate, a remaining first gate insulating layer, a second gate and a remaining second gate insulating layer. The remaining first gate insulating layer not covered by the first gate has a first thickness, and the remaining second gate insulating layer not covered by the second gate has a second thickness, wherein a ratio between the first thickness and the second thickness is about 10 to 20. A pair of first spacers and a pair of second spacers are formed on sidewalls of the first gate and the second gate, respectively.

Semiconductor device fabricating method

A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.

Semiconductor device and fabrication method thereof

A gate process and a gate process for an embedded memory device. A semiconductor silicon substrate has a memory cell area and a logic circuit area. A first dielectric layer is formed overlying the semiconductor silicon substrate, and then a gate structure is formed overlying the first dielectric layer of the memory cell area. Next, a protective layer is formed overlying the first dielectric layer and the top and sidewall of the gate structure. Next, an insulating spacer is formed overlying the protective layer disposed overlying the sidewall of the gate structure. Next, a pre-cleaning process is performed to remove the protective layer and the first dielectric layer overlying the logic circuit area. Next, a second dielectric layer is formed overlying the logic circuit area, and then a gate layer is formed overlying the second dielectric layer of the logic circuit area.

Gate process and gate structure for an embedded memory device

A high-voltage device with improved punch through voltage. A semiconductor silicon substrate has a high-voltage device region on which a gate structure is patterned. A lightly doped region is formed in the substrate and lateral to the gate structure. A spacer is formed on the sidewall of the gate structure. A heavily doped region is formed in the lightly doped region and lateral to the spacer. A lateral distance is kept between the spacer and the heavily doped region.

High-voltage device with improved punch through voltage and process for same compatible with low-voltage device process

A method of forming and recognizing an identification mark for read-only memory. First, a first patterned resist layer is formed on a semiconductor substrate having an insulating region and a device region thereon by a code mask having code and identification mark patterns, and the identification mark pattern is over the insulating region. Next, ion implantation is performed to code in the device region. Thereafter, a second patterned resist layer is formed on the first patterned resist layer by a common mask to expose the entire identification mark pattern of the first patterned resist layer only. The identification mark pattern is then transferred to the insulating region by dry etching. Finally, the substrate having a clear identification mark is placed in an optical microscope for identification by an operator.

Method of forming and recognizing an identification mark for read-only memory

A process for fabricating a straight walled, silicon nitride capped, gate structure, for a MOSFET device, has been developed. The process features the creation of a straight walled, photoresist shape, to be used as an etch mask, during the patterning of the straight walled, silicon nitride capped, gate structure. A silicon oxynitride layer, with a specific thickness range between about 820 to 920 Angstroms, is used as a bottom anti-reflective coating, (BARC), layer, located between an overlying straight walled, photoresist shape, and an underlying silicon nitride capping layer. The BARC layer retards the reflection emitted from a silicon nitride capping layer, during the photolithographic exposure procedure, used for definition of the straight walled, photoresist shape, allowing the desired straight walled, photoresist shape, to be obtained, independent of the thickness of the silicon nitride capping layer. The ability to fabricate straight walled, silicon nitride capped, gate structures, allows control, and uniformity, of channel regions, located underlying the straight walled, silicon nitride capped, gate structure, and between source/drain regions, self-aligned to the straight walled, silicon nitride capped, gate structures, to be realized.

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Hsinchu, Taiwan

Hsiao-Ying Yang