TSMC Solid State Lighting Ltd.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Visera Technologies Company Limited

Industrial Technology Research Institute

Epistar Corporation

National Sun Yat-sen University of Kaohsiung

Omnivision Technologies, Inc.

Hsiao-Wen Lee

Min-Sheng Wu

Chi-Xiang Tseng

Shin-Puu Jeng

Hsien-Wen Liu

Jui-Ping Weng

Tien-Ming Lin

Tien-Min Lin

Chi Xiang Tseng

Shih-Yi Wen

Shuo-Mao Chen

Feng-Cheng Hsu

Tzu-Han Lin

Yu-Sheng Tang

Han-Hsiang Huang

Shang-Yu Tsai

Han-Ping Pu

Ming-Hung Chen

Wu-Cheng Kuo

Chih-Hsuan Sun

Sheng-Lung Huang

Sheng-Shin Guo

Wei-Yu Yeh

Chia-Yang Chang

Pei-Wen Ko

Sheng-Pan Huang

Pai-Chun Peter Zung

Chia-Yao Lo

Chien-Pang Lin

Kwang-Yao Huang

Sun-Bin Yin

Shih-Yu Tu

Hsin-Hung Chen

Chung Yu Wang

Ching-Yi Chen

Tzy-Ying Lin

Hao-Yu Yang

Jung-Tang Chu

Bing-Ru Chen

Li-Ding Wei

Hao-Wei Ku

Peter Zung

Kuo-Chung Yee

Chyi Shyuan Chern

Kazuaki Hashimoto

Hsiu-Mei Yu

Hsin-Hsien Wu

Teng-Sheng Chen

Chieh Hu

Chien-Liang Yeh

Hsueh-Hung Fu

Wu-Chieh Liu

Hsin-Hsien Lee

Chun-Chih Chang

Fu-Wen Liu

Yu-Han Chien

Jin-Hua Wang

Huai-En Lai

Chih-Chiang Ho

Wen-I Wu

Bii-Cheng Chang

Chia-Chang Kuo

Li-Min Lee

Sheng Bang Huang

Yeh-I Su

Chin-Chen Kuo

Tsai-Shuan Chou

Chen-Yu Weng

Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

Multi-chip packages and methods of forming the same

The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.

Integrated fan-out packaging

Package structures are provided. A package structure includes an adhesive layer and a semiconductor substrate over the adhesive layer. The package structure also includes a connector over the semiconductor substrate. The package structure further includes a first buffer layer surrounding the connector and the semiconductor substrate and covering the adhesive layer. An interface between the adhesive layer and the first buffer layer is substantially level with a bottom surface of the semiconductor substrate. In addition, the package structure includes an encapsulation layer surrounding the first buffer layer. The package structure also includes a redistribution layer over the first buffer layer and the encapsulation layer.

Package structure

Multi-chip packages

Multi-chip wafer level packages

Methods of forming multi-chip wafer level packages

Package structures are provided. A package structure includes an adhesive layer and a semiconductor substrate over the adhesive layer. The package structure also includes a connector over the semiconductor substrate. The package structure further includes a first buffer layer surrounding the connector. In addition, the package structure includes an encapsulation layer surrounding the first buffer layer. The first buffer layer is sandwiched between the encapsulation layer and the semiconductor substrate, and a sidewall of the encapsulation layer is in direct contact with a sidewall of the first buffer layer and a sidewall of the adhesive layer. The package structure also includes a redistribution layer over the first buffer layer and the encapsulation layer.

Package structure with buffer layer sandwiched between encapsulation layer and semiconductor substrate

The present disclosure provides a semiconductor structure including a first insulation, a second insulation over the first insulation, a third insulation over the second insulation, a first conductor proximal to a boundary between the first insulation and the second insulation, and an electronic device electrically connected to the first conductor and at least partially surrounded by the second insulation. A coefficient of thermal expansion (CTE) of the second insulation is larger than a CTE of the first insulation and larger than a CTE of the third insulation.

Semiconductor structure and manufacturing method thereof

Multi-chip wafer level packages and methods of forming the same

Package structures and methods for forming the same are provided. A fan-out package structure includes a semiconductor substrate. The package structure also includes a connector over a top surface of the semiconductor substrate. The package structure further includes a buffer layer surrounding the connector and overlying a sidewall of the semiconductor substrate. In addition, the package structure includes an encapsulation layer surrounding the buffer layer. The buffer layer is between the encapsulation layer and the sidewall of the semiconductor substrate. The package structure also includes a redistribution layer (RDL) over the buffer layer and the encapsulation layer. The redistribution layer is electrically connected to the connector.

Package structure and method for forming the same

A complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) package is provided. The image sensor package comprises a first integrated circuit (IC) die, a second IC die, and a fan-out structure. The first IC die comprises a pixel sensor array, and the second IC die is under and bonded to the first IC die. Further, the fan-out structure is under and bonded to the second IC die. The fan-out structure comprises a third IC die, a fan-out dielectric layer laterally adjacent to the third IC die, a through insulator via (TIV) extending through the fan-out dielectric layer, and one or more redistribution layers (RDLs) under the third IC die and the TIV. The one or more RDLs electrically couple to the third IC die and the TIV. A method for manufacturing the CIS package is also provided.

Complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) package with an image buffer

A light emitting diode (LED) with a micro-structure lens includes a LED die and a micro-structure lens. The micro-structure lens includes a convex lens portion, at least one concentric ridge structure surrounding the convex lens portion, and a lower portion below the convex lens portion and the at least one concentric ridge structure. The lower portion is arranged to be disposed over the LED die. A first optical path length from an edge of the LED die to a top center of the microstructure lens is substantially the same as a second optical path length from the edge of the LED die to a side of the micro-structure lens.

Method of fabricating light-emitting diode with a micro-structure lens

Growing community of inventors

Hsinchu, Taiwan

Hsiao-Wen Lee