Promos Technologies, Inc

Other

Inotera Memories, Inc.

Hsiao-Lei Wang

Sheng-Fen Chiu

Jesse Chung

Yueh-Chuan Lee

Hung-Kwei Liao

Shih-Lung Chen

Kao-Mei Sung

Chao-Hsi (Jesse) Cheng

Hwei-Lin Chuang

Chih-Hung Liao

Chao-Chueh Wu

Po-Yen Liu

An encapsulated substrate includes a zinc oxide substrate and a composite barrier layer. The composite barrier layer includes a first film layer having a first material different from zinc oxide, a second film layer covered on a surface of the first film layer and having a second material different from the zinc oxide and the first material, and an active layer formed on the composite barrier layer and corresponding to an acting surface of a zinc oxide substrate and having an acting material different from the zinc oxide.

Encapsulated substrate, manufacturing method, high band-gap device having encapsulated substrate

A method of manufacturing low parasitic capacitance bit line for stack DRAM, comprising the following steps: offering a semi-conductor base, which semi-conductor having already included an oxide, plural word line stacks, plural bit line stacks and plural polysilicons; applying a multi layer resist coat; removing the multi layer resist coat and further removing parts of the oxide located on the polysilicon to form contact holes exposing the plural polysilicons; depositing an oxide layer; etching the oxide layer to form the oxide layer spacer; depositing a polysilicon layer; performing lithography and etching on the polysilicon layer thereby allowing the rest of the polysilicon layer that is column-shaped to form capacitor contacts; and using another oxide to fill into the space among the word line stacks and the capacitor contacts.

Low parasitic capacitance bit line process for stack DRAM

A method of increasing DRAM cell capacitance via formation of deep, wide diameter trench capacitor structures, has been developed. An underlying semiconductor substrate is used to accommodate deep, wide diameter trench capacitor structures while an overlying, bonded, thinned semiconductor substrate is used to accommodate narrow diameter trench structures, in turn used for communication to the underlying deep trench capacitor structures, as well as to accommodate the elements of the DRAM device, such as the transfer gate transistors. The use of an underlying semiconductor substrate for accommodation of the trench capacitor structures allows a wider diameter structures to be used, thus reducing patterning difficulties encountered when forming narrow diameter, deep trench capacitor structures.

Aggressive capacitor array cell layout for narrow diameter DRAM trench capacitor structures via SOI technology

A method of manufacturing a deep trench capacitor. A deep trench is formed in a substrate. A conformal capacitor dielectric layer and a first conductive layer are sequentially formed, completely filling the deep trench. The first conductive layer has a seam. The first conductive layer is etched to open up the seam. A collar oxide layer is formed over the interior surface of the deep trench. A collar liner layer is formed over the collar oxide layer inside the deep trench. Using the collar liner layer as a mask, the collar oxide material above the first conductive layer and within the seam is removed. The collar liner layer is removed. Finally, a second conductive layer and a third conductive layer are sequentially formed inside the deep trench.

Method of manufacturing deep trench capacitor

A method for manufacturing a deep trench capacitor, which includes forming a layer of silicon nitride over a silicon substrate, depositing a layer of borosilicate glass having a predetermined thickness over the layer of silicon nitride, patterning and defining the layer of borosilicate glass to expose two regions of the silicon substrate separated by a sacrificial mask, wherein the sacrificial mask includes the layer of borosilicate glass and the layer of silicon nitride, etching the two regions of the silicon substrate to form two trenches, wherein the predetermined thickness of the layer of borosilicate glass allows the sacrificial mask and a portion of the silicon substrate beneath the sacrificial mask to be removed, depositing a layer of silicon nitride on the sidewalls of the trenches, and depositing doped polysilicon into the trenches to form a single capacitor.

Method for forming a trench capacitor

A method is achieved for making improved deep trench capacitors for DRAM circuits with reduced trench faceting at the wafer edge and improved pad silicon nitride (Si N ) uniformity for increasing process yields. The method utilizes a thicker pad Si N as part of a hard mask used to etch the deep trenches. Then, after forming the deep trench capacitors by a sequence of process steps a shallow trench isolation (STI) is formed. The method utilizes etching shallow trenches in the same thicker pad Si N layer and into the silicon substrate. A second insulating layer is deposited and polished back (CMP) into the pad Si N layer. A key feature is to use a second mask to protect the substrate center while partially etching back the thicker portion of pad Si N layer at the substrate edge inherently resulting from the CMP. This minimizes the nonuniformity of the pad Si N layer to provide a more reliable structure for further processing.

Method for making deep trench capacitors for DRAMs with reduced faceting at the substrate edge and providing a more uniform pad Si3N4layer across the substrate

Growing community of inventors

Tainan, Taiwan

Hsiao-Lei Wang