Taiwan Semiconductor Manufacturing Comp. Ltd.

Hsiao-Kang Chang

Shau-Lin Shue

Hsin-Yen Huang

Shao-Kuan Lee

Cheng-Chin Lee

Cherng-Shiaw Tsai

Ting-Ya Lo

Chi-Lin Teng

Kai-Fang Cheng

Kuang-Wei Yang

Ming-Hsien Lin

Gary Liu

Ming-Han Lee

Chia-Tien Wu

Hsin-Ping Chen

Chuan-Pu Chou

A method for manufacturing a semiconductor device includes preparing an electrically conductive structure including a plurality of electrically conductive features, conformally forming a thermally conductive dielectric capping layer on the electrically conductive structure, conformally forming a dielectric coating layer on the thermally conductive dielectric capping layer, filling a sacrificial material into recesses among the electrically conductive features, recessing the sacrificial material to form sacrificial features in the recesses, forming a sustaining layer over the dielectric coating layer to cover the sacrificial features, and removing the sacrificial features to form air gaps covered by the sustaining layer. The thermally conductive dielectric capping layer has a thermal conductivity higher than that of the dielectric coating layer.

Semiconductor device having thermally conductive air gap structure and method for manufacturing the same

An interconnect structure includes a dielectric layer, a first conductive feature, a hard mask layer, a conductive layer, and a capping layer. The first conductive feature is disposed in the dielectric layer. The hard mask layer is disposed on the first conductive feature. The conductive layer includes a first portion and a second portion, the first portion of the conductive layer is disposed over at least a first portion of the hard mask layer, and the second portion of the conductive layer is disposed over the dielectric layer. The hard mask layer and the conductive layer are formed by different materials. The capping layer is disposed on the dielectric layer and the conductive layer.

Semiconductor interconnection structure and methods of forming the same

A method for manufacturing a semiconductor device includes: forming a first feature and a second feature extending in a normal direction transverse to a substrate; directionally depositing a dielectric material upon the features at an inclined angle relative to the normal direction so as to form a cap layer including a top portion disposed on a top surface of each of the features, and two opposite wall portions extending downwardly from two opposite ends of the top portion to partially cover two opposite lateral surfaces of each of the features, respectively, the cap layer on the first feature being spaced apart from the cap layer on the second feature; forming a sacrificial feature in a recess between the features; forming a sustaining layer to cover the sacrificial feature; and removing the sacrificial feature to form an air gap.

Semiconductor device having metallization layer with low capacitance and method for manufacturing the same

An interconnection structure includes a first dielectric layer, a first conductive layer disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer, a second conductive layer disposed in the second dielectric layer in electrical contact with the first conductive layer, a third dielectric layer formed over the second dielectric layer, wherein the third dielectric layer comprises silicon carbon-nitride (SiCN) based material, and a resistor device disposed in the third dielectric layer.

Semiconductor interconnection structures comprising a resistor device and methods of forming the same

A semiconductor structure includes a base structure, a plurality of electrically conductive features disposed on the base structure, and an isolation structure disposed on the base structure. The base structure includes a substrate. The electrically conductive features are spaced apart from each other. The isolation structure includes a first inter-metal dielectric feature extending horizontally to interconnect the electrically conductive features, a first air gap layer disposed in the isolation structure and around the electrically conductive features, and a first sustaining feature extending horizontally to interconnect the electrically conductive features and disposed between the first inter-metal dielectric feature and the first air gap layer. Methods for manufacturing the semiconductor structure are also disclosed.

Semiconductor structure with air gap and method for manufacturing the same

A semiconductor structure is provided. The semiconductor structure includes a substrate and a device region formed over the substrate. The semiconductor structure further includes an interconnect structure formed over the device region and a first passivation layer formed over the interconnect structure. The semiconductor structure also includes a metal pad formed over and extending into the first passivation layer and a second passivation layer formed over the first passivation layer. The second passivation layer includes a thermal conductive material, and the thermal conductivity of the thermal conductive material is higher than 4 W/mK.

Semiconductor structure with improved heat dissipation

A method for manufacturing a semiconductor structure includes: forming a dielectric layer on a base structure; forming a trench in the dielectric layer to expose the base structure; forming a metal contact in the trench; and performing a plurality of first atomic layer deposition (ALD) cycles to form a plurality of first atomic layers which cover the dielectric layer and the metal contact and which serve as an etch stop layer. Each of the first ALD cycles includes: forming a corresponding one of the first atomic layers; and performing a treatment to convert the corresponding first atomic layer into monocrystalline phase at a temperature not greater than 425° C.

Method for manufacturing semiconductor structure with material in monocrystalline phase

A first dielectric layer is formed on a semiconductor structure. The first dielectric layer has a hardness higher than 10 GPa and a dielectric constant in a range between 1.0 and 4.0. A trench is formed in the first dielectric layer. A conductive feature is formed in the trench in contact with the semiconductor structure. A second dielectric layer is formed over the first dielectric layer and the conductive feature. A via structure is formed in the second dielectric layer in contact with the conductive feature.

Semiconductor interconnection structures and methods of forming the same

An interconnection structure includes a first dielectric layer, a first conductive feature, a first liner layer, a second conductive feature, a second liner layer, and an air gap. The first conductive feature is disposed in the first dielectric layer. The first liner layer is disposed between the first conductive feature and the first dielectric layer. The second conductive feature penetrates the first dielectric layer. The second liner layer is disposed between the second conductive feature and the first dielectric layer. The air gap is disposed in the first dielectric layer between the first liner layer and the second liner layer. The first liner layer and the second liner layer include metal oxide, metal nitride, or silicon oxide doped carbide.

A semiconductor device package, along with methods of forming such, are described. The semiconductor device package includes a first semiconductor device structure having a first substrate, two first devices disposed on the first substrate, a first interconnection structure disposed over the first substrate and the two first devices, and a first thermal feature disposed through the first substrate and the first interconnection structure. The semiconductor device package further includes a second semiconductor device structure disposed over the first semiconductor device structure having a second interconnection structure disposed over the first interconnection structure, a second substrate disposed over the second interconnection structure, two second devices disposed between the second substrate and the second interconnection structure, and a second thermal feature disposed through the second substrate and the second interconnection structure. The second thermal feature is in contact with the first thermal feature.

Semiconductor device package including a thermal conductive layer and methods of forming the same

In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.

Thermal interconnect structure for thermal management of electrical interconnect structure

An interconnection structure includes a first dielectric layer, a first conductive feature, a second dielectric layer, a conductive layer, a liner layer, a third dielectric layer, a second conductive feature, and a first capping layer. The first conductive feature is disposed in the first dielectric layer. The second dielectric layer is formed on the first dielectric layer, and the second dielectric layer is in direct contact with the first dielectric layer. The conductive layer is disposed in the second dielectric layer. The liner layer is disposed between the conductive layer and the second dielectric layer. The third dielectric layer is formed on the second dielectric layer. The second conductive feature is disposed in the third dielectric layer. The first capping layer is disposed between the second conductive feature and the third dielectric layer.

A method for forming an interconnect structure is described. In some embodiments, the method includes forming a conductive layer, removing portions of the conductive layer to form a via portion extending upward from a bottom portion, forming a sacrificial layer over the via portion and the bottom portion, recessing the sacrificial layer to a level substantially the same or below a level of a top surface of the bottom portion, forming a first dielectric material over the via portion, the bottom portion, and the sacrificial layer, and removing the sacrificial layer to form an air gap adjacent the bottom portion.

Interconnect structure and methods of forming the same

A semiconductor structure includes a substrate with a conductive structure thereon, a first dielectric layer, a conductive feature and a second dielectric layer. The substrate includes a conductive feature. The conductive feature is formed in the first dielectric layer, is electrically connected to the conductive feature. The second dielectric layer is formed on the first dielectric layer and is disposed adjacent to the conductive feature. The first dielectric layer and the second dielectric layer are made of different materials.

Semiconductor structure having dielectric-on-dielectric structure and method for forming the semiconductor structure

Contact structures and methods of forming the same are provided. A contact structure according to the present disclosure includes an etch stop layer (ESL), a first pillar feature and a second pillar feature disposed on the ESL, a metal feature disposed between the first pillar feature and the second pillar feature, the metal feature including a first sidewall, a bottom surface, a second sidewall, and a top surface, a dielectric liner extending continuously from a top surface of the first pillar feature, along the first sidewall, the bottom surface and the second sidewall of the metal feature, and onto a top surface of the second pillar feature, and a gap between the first pillar feature and a portion of the dielectric liner that extends along the first sidewall of the metal feature.

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Hsinchu, Taiwan

Hsiao-Kang Chang