Advanced Semiconductor Engineering, Inc.

Hsiang-Ming Feng

Sheng-Ming Wang

Kuang-Hsiung Chen

Tien-Szu Chen

Yu-Ying Lee

Wen-Chih Shen

Hsing-Wen Lee

Bing-Yun Cheng

Yen-Hua Kuo

Mei-Lin Hsieh

The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.

Semiconductor package and method of manufacturing the same

An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices is attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages.

Heat dissipating semiconductor device packages and related methods

The substrate includes a first dielectric layer, a first circuit pattern, a plurality of pillars and a second circuit pattern. The first dielectric layer has opposing first and second dielectric surfaces. The first circuit pattern is embedded in the first dielectric layer and defines a plurality of curved trace surfaces. Each of the pillars has an exterior surface adapted for making external electrical connection and a curved base surface abutting a corresponding one of the trace surfaces. The second circuit pattern is on the second dielectric surface of the first dielectric layer and electrically connected to the first circuit pattern.

Semiconductor package substrates having pillars and related methods

An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices are attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages.

Heat dissipating semiconductor device packages

The package substrate includes a core, a plurality of first circuit segments, and a plurality of conductive pillars. Each of the first circuit segments has a patterned metal layer disposed on the core, a barrier layer disposed on the patterned metal layer, and an upper metal pattern disposed on the barrier layer. The conductive pillars penetrate the core, the patterned metal layer, and the barrier layer, and contact the upper metal pattern. The conductive pillars are formed from a material that can be selectively removed without affecting the barrier layer.

Semiconductor package substrates having layered circuit segments, and related methods

A Quad Flat No Leads (QFN) package includes a lead frame, a chip, an encapsulant, and a protective layer. The lead frame includes a plurality of leads. Each of the leads has a lower surface that is divided into a contact area and a non-contact area. The chip is configured on and electrically connected to the lead frame. The encapsulant encapsulates the chip and the leads and fills spaces between the leads. The contact areas and the non-contact areas of the leads are exposed by the encapsulant. The protective layer covers the non-contact areas of the leads.

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Tainan, Taiwan

Hsiang-Ming Feng