Taiwan Semiconductor Manufacturing Comp. Ltd.

Hsi-Wen Tien

Chung-Ju Lee

Wei-Hao Liao

Chih Wei Lu

Hsin-Chieh Yao

Yu-Teng Dai

Pin-Ren Dai

Chih-Wei Lu

Shau-Lin Shue

Chia-Tien Wu

Hsin-Yen Huang

An MRAM device includes a bottom electrode over a substrate, a magnetic tunnel junction (MTJ) structure on the bottom electrode and a top electrode on the MTJ structure. The MRAM device also includes spacers on sidewalls of the top electrode and the MTJ structure. The MRAM device further includes a first etch stop layer on the spacers. A bottommost surface of the first etch stop layer covers a topmost surface of the spacers. In addition, the MRAM device includes a top electrode via on the top electrode and the first etch stop layer.

Magneto-resistive random-access memory (MRAM) devices with self-aligned top electrode via

The present disclosure relates to an integrated chip including a substrate. A first conductive wire is within a first dielectric layer that is over the substrate. A first etch-stop layer is over the first dielectric layer. A second etch-stop layer is over the first etch-stop layer. A conductive via is within a second dielectric layer that is over the second etch-stop layer. The conductive via extends through the second etch-stop layer and along the first etch-stop layer to the first conductive wire. A first lower surface of the second etch-stop layer is on a top surface of the first etch-stop layer. A second lower surface of the second etch-stop layer is on a top surface of the first conductive wire.

Dual etch-stop layer structure

Some embodiments of the present disclosure relate to a semiconductor structure including a first conductive wire disposed over a substrate. A dielectric liner is arranged along sidewalls and an upper surface of the first conductive wire and is laterally surrounded by a first dielectric layer. The dielectric liner and the first dielectric layer are different materials. A conductive via is disposed within a second dielectric layer over the first conductive wire. The conductive via has a first lower surface disposed over the first dielectric layer and a second lower surface below the first lower surface and over the first conductive wire.

Self-assembled dielectric on metal rie lines to increase reliability

The present disclosure relates to a semiconductor structure including an interconnect structure disposed over a semiconductor substrate. A lower metal line is disposed at a first height over the semiconductor substrate and extends through a first interlayer dielectric layer. A second interlayer dielectric layer is disposed at a second height over the semiconductor substrate and comprises a first dielectric material. An upper metal line is disposed at a third height over the semiconductor substrate. A via is disposed at the second height. The via extends between the lower metal line and the upper metal line. A protective dielectric structure is disposed at the second height. The protective dielectric structure comprises a protective dielectric material and is disposed along a first set of opposing sidewalls of the via, the protective dielectric material differing from the first dielectric material.

Self-aligned interconnect structure

In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a dielectric on wire structure is arranged directly over the interconnect wire. Outer sidewalls of the dielectric on wire structure are surrounded by the first interconnect dielectric layer. The integrated chip further includes a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect via that extends through the second interconnect dielectric layer and the dielectric on wire structure to contact the interconnect wire.

Dielectric on wire structure to increase processing window for overlying via

In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate, a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect conductive structure arranged within the second interconnect dielectric layer. The interconnect conductive structure includes an outer portion that includes a first conductive material. Further, the interconnect conductive structure includes a central portion having outermost sidewalls surrounding by the outer portion of the interconnect conductive structure. The central portion includes a second conductive material different than the first conductive material.

Interconnect conductive structure comprising two conductive materials

The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.

Integrated chip with an etch-stop layer forming a cavity

In one embodiment, a method of forming metal interconnects uses a direct metal etch approach to form and fill the metal gap. The method may include directly etching a metal layer to form metal patterns. The metal patterns may be spaced apart from one another by recesses. A dielectric spacer may be formed extending along the sidewalls of each of the recesses. The recesses may be filled with a conductive material to form a second set of metal patterns. By directly etching the metal film, the technique allows for reduced line width roughness. The disclosed structure may have the advantages of increased reliability, better RC performance and reduced parasitic capacitance.

Double patterning approach by direct metal etch

The present disclosure relates to an integrated chip comprising a substrate. A first conductive wire is over the substrate. A second conductive wire is over the substrate and is adjacent to the first conductive wire. A first dielectric cap is laterally between the first conductive wire and the second conductive wire. The first dielectric cap laterally separates the first conductive wire from the second conductive wire. The first dielectric cap includes a first dielectric material. A first cavity is directly below the first dielectric cap and is laterally between the first conductive wire and the second conductive wire. The first cavity is defined by one or more surfaces of the first dielectric cap.

Integrated chip with inter-wire cavities

A semiconductor arrangement is provided. The semiconductor arrangement includes a first dielectric layer over a substrate, a metal layer over the first dielectric layer, a first conductive structure passing through the metal layer and the first dielectric layer, a second conductive structure passing through the metal layer and the first dielectric layer, and a third conductive structure coupling the first conductive structure to the second conductive structure, and overlying a first portion of the metal layer between the first conductive structure and the second conductive structure, wherein an interface exists between the metal layer and at least one of the first conductive structure or the second conductive structure.

Semiconductor arrangement and method of making

In some embodiments, the present disclosure relates to a method of forming an interconnect. The method includes forming an etch stop layer (ESL) over a lower conductive structure and forming one or more dielectric layers over the ESL. A first patterning process is performed on the one or more dielectric layers to form interconnect opening and a second patterning process is performed on the one or more dielectric layers to increase a depth of the interconnect opening and expose an upper surface of the ESL. A protective layer is selectively formed on sidewalls of the one or more dielectric layers forming the interconnect opening. A third patterning process is performed to remove portions of the ESL that are uncovered by the one or more dielectric layers and the protective layer and to expose the lower conductive structure. A conductive material is formed within the interconnect opening.

Selective deposition of a protective layer to reduce interconnect structure critical dimensions

In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.

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Hsi-Wen Tien