Taiwan Semiconductor Manufacturing Comp. Ltd.

Hsi-Wen Tien

Chung-Ju Lee

Wei-Hao Liao

Pin-Ren Dai

Chih-Wei Lu

Chih Wei Lu

Hsin-Chieh Yao

Yu-Teng Dai

Shau-Lin Shue

Ming-Han Lee

Shin-Yi Yang

Hsiang-Huan Lee

David Dai

Chung-Te Lin

Carlos H Diaz

Tien-I Bao

Chien-Min Lee

Tai-Yen Peng

Yung-Hsu Wu

Chia-Tien Wu

Hsin-Yen Huang

Cheng-Hsiung Tsai

Chien-Hua Huang

Chia-Wei Su

Cherng-Shiaw Tsai

Hwei-Jay Chu

Embodiments of the present disclosure relates to a method for forming a semiconductor device structure. The method includes including forming one or more conductive features in a first interlayer dielectric (ILD), forming an etch stop layer on the first ILD, forming a second ILD over the etch stop layer, forming one or more openings through the second ILD and the etch stop layer to expose a top surface of the one or more first conductive features, wherein the one or more openings are formed by a first etch process in a first process chamber, exposing the one or more openings to a second etch process in a second process chamber so that the shape of the or more openings is elongated, and filling the one or more openings with a conductive material.

Semiconductor device structure and methods of forming the same

An interconnect structure includes a dielectric layer, a first conductive feature, a second conductive feature, a third conductive feature, and a dielectric fill. The first conductive feature is disposed in the dielectric layer. The second conductive feature is disposed over the first conductive feature. The second conductive feature includes a first conductive layer disposed over the first conductive feature, a second conductive layer disposed on the first conductive layer, and a third conductive layer disposed on the second conductive layer. The first conductive layer, the second conductive layer and the third conductive layer have substantially the same width. The third conductive feature is disposed over the dielectric layer. The dielectric fill is disposed over the dielectric layer between the second conductive feature and the third conductive feature.

Interconnection structure and methods of forming the same

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises receiving a structure including a substrate and a first hard mask over the substrate, the first hard mask having at least two separate portions; forming spacers along sidewalls of the at least two portions of the first hard mask with a space between the spacers; forming a second hard mask in the space; forming a first cut in the at least two portions of the first hard mask; forming a second cut in the second hard mask; and depositing a cut hard mask in the first cut and the second cut.

Method and structure of cut end with self-aligned double patterning

A semiconductor structure includes a conductive feature disposed over a semiconductor substrate, a via disposed in a first interlayer dielectric (ILD) layer over the conductive feature, and a metal-containing etch-stop layer (ESL) disposed on the via, where the metal-containing ESL includes a first metal and is resistant to etching by a fluorine-containing etchant. The semiconductor structure further includes a conductive line disposed over the metal-containing ESL, where the conductive line includes a second metal different from the first metal and is etchable by the fluorine-containing etchant, and where the via is configured to interconnect the conductive line to the conductive feature. Furthermore, the semiconductor structure includes a second ILD layer disposed over the first ILD layer.

Methods of etching metals in semiconductor devices

A memory device includes a bottom electrode, a tunneling junction disposed over the bottom electrode, and a top electrode disposed over the tunneling junction. The top electrode includes a first top electrode layer and a second top electrode layer above the first top electrode layer. The first and second top electrode layers include different material compositions. The first top electrode layer is thinner than the tunneling junction, and the second top electrode layer is thicker than the tunneling junction.

Structure and method for an MRAM device with a multi-layer top electrode

A device includes a first dielectric layer, a magnetic tunnel junction (MTJ), an oxide layer, a cap layer, and a second dielectric layer. The MTJ is over the first dielectric layer. The oxide layer is over the first dielectric layer. The cap layer is over the first dielectric layer. The cap layer is in contact with a sidewall of the MTJ and a sidewall of the oxide layer. The second dielectric layer is over the cap layer.

Magnetic tunnel junction devices

A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a conductive line over the substrate. The semiconductor device structure also includes a catalyst structure over the conductive line and a carbon-containing conductive via directly on the catalyst structure. The semiconductor device structure further includes a dielectric layer surrounding the carbon-containing conductive via.

Structure and formation method of semiconductor device with carbon-containing conductive structure

An interconnection structure, along with methods of forming such, are described. The interconnection structure includes a first portion of a conductive layer, a second portion of the conductive layer disposed adjacent the first portion of the conductive layer, and a dielectric foam disposed between the first and second portions of the conductive layer. The dielectric foam includes fluid gaps filled with carbon dioxide gas.

A method of forming a semiconductor device structure is provided. The method includes forming a masking structure with first openings over a semiconductor substrate and correspondingly forming metal layers in the first openings. The method also includes recessing the masking structure to form second openings between the metal layers and forming a sacrificial layer surrounded by a first liner in each of the second openings. In addition, after forming a second liner over the sacrificial layer in each of the second openings, the method includes removing the sacrificial layer in each of the second openings to form a plurality of air gaps therefrom.

Semiconductor device structure having air gap and method for forming the same

A device includes a semiconductor substrate, a bottom conductive line, a bottom electrode, a magnetic tunneling junction (MTJ), and a residue. The bottom conductive line is over the semiconductor substrate. The bottom electrode is over the bottom conductive line. The MTJ is over the bottom electrode. The residue of the MTJ is on the sidewall of the bottom electrode and is spaced apart from the bottom conductive line.

An semiconductor device includes a first dielectric layer, an etch stop layer, an interconnect structure, and a second dielectric layer. The etch stop layer is over the first dielectric layer. The interconnect structure includes a conductive via in the first dielectric layer and the etch stop layer, a conductive line over the conductive via, an intermediate conductive layer over the conductive line, and a conductive pillar over the intermediate conductive layer. The interconnect structure is electrically conductive at least from a top of the conductive pillar to a bottom of the conductive via. The second dielectric layer surrounds the conductive line, the intermediate conductive layer, and the conductive pillar, wherein a bottom of the second dielectric layer is lower than a top of the conductive line, and a top of the second dielectric layer is higher than the top of the conductive line.

Semiconductor device

Some embodiments relate to a method for forming a semiconductor structure, the method includes forming a first dielectric layer over a substrate. A first conductive wire is formed over the first dielectric layer. A spacer structure is formed over the first conductive wire. The spacer structure is disposed along sidewalls of the first conductive wire. A second dielectric layer is deposited over and around the first conductive wire. The spacer structure is spaced between the first conductive wire and the second dielectric layer. A removal process is performed on the spacer structure and the second dielectric layer. An upper surface of the spacer structure is disposed above an upper surface of the first conductive wire.

Sidewall spacer structure enclosing conductive wire sidewalls to increase reliability

An integrated circuit includes a substrate, a bottom electrode, a dielectric layer, a metal-containing compound layer, a resistance switching element, and a top electrode. The bottom electrode is over the substrate, the bottom electrode having a bottom portion and a top portion over the bottom portion. The bottom portion of the bottom electrode has a sidewall slanted with respect to a sidewall of the top portion of the bottom electrode. The dielectric layer surrounds the bottom portion of the bottom electrode. The metal-containing compound layer surrounds the top portion of the bottom electrode. A top end of the sidewall of the bottom portion of the bottom electrode is higher than a bottom surface of the metal-containing compound layer. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element.

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Hsi-Wen Tien