Teradyne, Inc.

Howard Lin

Ronald A Sartschev

Michael C Panis

Jan Paul Anthonie Van Der Wagt

Corbin L Champion

Scott D Schaber

An example system is for testing a device under test (DUT) that includes a first core and a second core. The system includes channels in parallel for connecting to a number of pins on the DUT. The channels are for sending test data to the DUT and for receiving measurement data from the DUT based on the test data. The measurement data includes time-division-multiplexed (TDM) data comprised of successive data packets received from the DUT over the channels as part of a bitstream. Each data packet includes a first number of bits from the first core and a second number of bits from the second core. Circuitry associated with the channels is configured to compare the measurement data with expected data, and to determine pass/fail status for the first core and for the second core based on the comparison.

Identifying failures in device cores

An example system includes first memory, second memory having a greater areal density than the first memory, and a logic circuit configured to move some test data from the second memory to the first memory while at least one of (i) reading other test data from the first memory or (ii) processing the other test data. The logic circuit is configured to process the other test data prior to output along a test channel. The test channel leads to a device under test (DUT) to be tested.

Managing memory in an electronic system

A semiconductor device-under-test (DUT) may be tested by an automated test system that processes test programs specifying a number of edges per tester cycle that may be greater than the number of edges the tester is capable of generating. The test system may include circuitry that reduces the number of edges in each cycle of a test program based on data specifying operation of the tester in that cycle and/or a prior cycle. Such a reduction simplifies the circuitry required to implement an edge generator by reducing the total number of timing verniers per channel. Nonetheless, flexibility in programming the test system is retained.

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Howard Lin