Yangtze Memory Technologies Co., Ltd.

Houde Zhou

Peng Chen

XinRu Zeng

Liquan Cai

Chao Gu

Meng Wang

BaoHua Zhang

Baohua Zhang

Xinru Zeng

The present disclosure provides a semiconductor structure, comprising a die/die stack attached on a substrate, a conductive top block covering a top surface of the die/die stack, and a plurality of ground wires conductively connect the conductive top block and to the substrate. The conductive top block, the plurality of ground wires, and the substrate form a Faraday cage to provide an electromagnetic interference shielding of the die/die stack.

Electromagnetic interference shielding package structures and fabricating methods thereof

A method for fabricating a substrate structure for packaging includes providing a core substrate, a plurality of conductive pads at a first surface of the core substrate, and a metal layer at a second surface of the core substrate opposite to the first surface; forming a conductive structure, for pasting the substrate structure onto an external component, on each of the plurality of conductive pads; forming a molding compound on the first surface of the core substrate and to encapsulate the conductive structure; and forming a plurality of packaging pads by patterning the metal layer at the second surface of the core substrate.

Substrate structure, and fabrication and packaging methods thereof

A semiconductor package structure includes a substrate, including first conductive pads and packaging pads opposite to the first conductive pads, one or more semiconductor chips stacking on the substrate, a molding compound encapsulating the semiconductor chips, first metal wires connecting the semiconductor chips to the packaging pads, a first metal pad on a side of the molding compound opposite to the substrate, and a second metal wire located in the molding compound and connecting the first metal pad to a chip-contact pad of a semiconductor chip of the semiconductor chips.

Semiconductor package structure and packaging method thereof

The present disclosure includes a semiconductor package including a redistribution layer (RDL) having a first surface in contact with input/output (I/O) contacts and a second surface opposite to the first surface. The semiconductor package also includes a staircase interconnect structure formed on the second surface of the RDL and electrically connected with the RDL. The staircase interconnect structure includes staircase layers including a first staircase layer and a second staircase layer stacked on a top surface of the first staircase layer. The second staircase layer covers a portion of the top surface of the first staircase layer such that a remaining portion of the top surface of the first staircase layer is exposed. Integrated circuit (IC) chips are electrically connected to the RDL via the staircase interconnect structure. A first IC chip of the IC chips is electrically connected to the RDL through the remaining portion of the top surface of the first staircase layer.

Flip-chip stacking structures and methods for forming the same

The present disclosure describes methods and systems for processing semiconductor wafers. A method for processing a wafer includes measuring one or more wafer characteristics of the wafer using a plurality of detectors. The wafer includes a device region and a perimeter region. The method also includes determining a wafer modification profile of the wafer based on the measured one or more wafer characteristics. The method further includes modifying a ring-shaped portion of the wafer within the perimeter region using the wafer modification profile. The modified ring-shaped portion has a penetration depth that is less than a thickness of the wafer. The method further includes performing a wafer thinning process on the wafer.

Method for processing semiconductor wafers

A chip package structure includes multiple chips stacked together, a molding layer encapsulating the multiple chips, a conductive layer is on a side of the molding layer away from the multiple chips, and a vertical conductive element extending from a surface of the molding layer to the bonding pad. Each of the multiple chips includes a bonding pad not covered by the multiple chips. The vertical conductive element connects the conductive layer and the bonding pad. The vertical conductive element includes gold.

Chip package structure and manufacturing method thereof

A laser system for dicing a semiconductor structure is disclosed. The laser system includes a laser source and a laser energy adjusting unit. The laser source is configured to generate a laser. The laser energy adjusting unit is movably provided on a laser light path between the laser source and the semiconductor structure. The laser energy adjusting unit is moved to the laser light path between the laser source and the semiconductor structure based on a first determination that the laser source is focused on a first preset region of the semiconductor structure having a first material.

Laser system for dicing semiconductor structure and operation method thereof

A laser dicing system is disclosed. The laser dicing system includes a host device and a laser source. The host device reads and identifies a mark formed on a surface of a semiconductor structure. The laser source is coupled to the host device and is configured to generate a dicing laser energy to form a trench on the semiconductor structure. The dicing laser energy irradiated on the semiconductor structure is adjustable based on information embedded in the mark.

Laser dicing system and method for dicing semiconductor structure including cutting street

A packaging method includes providing a substrate structure, including a core substrate, a plurality of first conductive pads at a first surface of the core substrate, and a plurality of packaging pads at a second surface of the core substrate; and packaging a plurality of semiconductor chips onto the substrate structure at the second surface of the core substrate, including forming a first metal wire to connect with a chip-contact pad of a semiconductor chip, and forming a molding compound on the second surface of the core substrate to encapsulate the plurality of semiconductor chips. One end of the first metal wire connects to the chip-contact pad, and another end of the first metal wire is exposed at the surface of the molding compound. The packaging method further includes forming a first metal pad on the surface of the molding compound to electrically connect with the first metal wire.

A chip package structure includes a chip stack and a redistribution layer. The chip stack includes multiple chips stacked together, a molding layer encapsulating the multiple chips, and a vertical conductive element extending from a surface of the molding layer reach and coupled to the bonding pad. Each of the multiple chips includes a bonding pad not covered by the multiple chips. The redistribution layer is above the molding layer and includes a conductive layer coupled to the vertical conductive element, and an insulating layer over and partially exposing the conductive layer.

A manufacturing method of an integrated circuit (IC) packaging structure includes the following steps. One or a plurality of dies is disposed on a packaging substrate. An encapsulation material is formed on the packaging substrate. The encapsulation material is configured to encapsulate the one or the plurality of the dies on the packaging substrate. At least one trench is formed in the encapsulation material. A heat dissipation structure is formed on the encapsulation material, and at least a part of the heat dissipation structure is formed in the at least one trench. The step of forming the heat dissipation structure includes the following steps. A first slurry is formed in the at least one trench, and a first curing process is performed to the first slurry for forming a first portion of the heat dissipation structure.

Manufacturing method of integrated circuit packaging structure

An electronic component includes a substrate comprising a die attach region and a perimeter region on a front side of the substrate; and at least one thermal indicator disposed within the perimeter region for monitoring the cumulative heat exposure of the substrate. The thermal indicator signals when the predetermined thermal budget limit that correlates with the decline in the condition of the OSP layer or the degradation of the adhesion of the die attach films is reached.

Electronic component comprising substrate with thermal indicator

A chip package structure including a first chip stack and a redistribution layer is provided. The first chip stack includes a plurality of first chips, a first molding layer and at least one first vertical conductive element. The plurality of first chips are sequentially stacked, wherein each of the plurality of first chips includes at least one first bonding pad, and the first bonding pads are not covered by the plurality of first chips. The first molding layer encapsulates the plurality of first chips. The at least one first vertical conductive element penetrates through the first molding layer, wherein the at least one first vertical conductive element is disposed on and electrically connected to at least one of the first bonding pads. The redistribution layer is disposed on the first chip stack and electrically connected to the at least one first vertical conductive element.

Growing community of inventors

Wuhan, China

Houde Zhou