International Business Machines Corporation

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Stmicroelectronics Gmbh

Samsung Electronics Co., Ltd.

Applied Materials, Inc.

Advanced Micro Devices Corporation

Chartered Semiconductor Manufacturing Ltd (corporation)

Adeia Semiconductor Solutions LLC

Hosadurga K Shobha

Son Van Nguyen

Deepika Priyadarshini

Lawrence Alfred Clevenger

Alfred Grill

Huai Huang

Daniel C Edelstein

Takeshi Nogami

Christopher J Penny

Benjamin David Briggs

Donald Francis Canaperi

Michael Rizzolo

Chih-Chao Yang

Nicholas Anthony Lanzillo

Thomas J Haigh, Jr

Yann Mignot

Sanjay C Mehta

Terry Allen Spooner

Koichi Motoyama

Cornelius Brown Peethala

Matthew T Shoudy

Junli Wang

Fee Li Lie

Shom Ponoth

Ekmini Anuja De Silva

Vamsi Krishna Paruchuri

Gauri V Karve

Muthumanickam Sankarapandian

Yongan Xu

Raghuveer Reddy Patlolla

Joe Lee

E Todd Ryan

Seth L Knupp

Joshua L Herman

Sampath Purushothaman

Robert Russell Robison

Qinghuang Lin

Elbert Emin Huang

David Lee Rath

Indira P Seshadri

John Christopher Arnold

Nicole A Saulnier

Leigh Anne H Clevenger

Isabel Cristina Chu

Ruilong Xie

David V Horak

Ruqiang Bao

Hsueh-Chung Chen

Gareth Geoffrey Hougham

Chi-Chun Liu

Kisik Choi

Griselda Bonilla

Satyanarayana Venkata Nitta

Stephen L Buchwalter

Cheng Chi

Roger Allan Quon

Shyng-Tsong Chen

Kaushik Chanda

Claudius Feger

James John Kelly

Wei Wang

Wenhui Wang

Joseph F Maniscalco

Kenneth Chun Kuen Cheng

Nancy C LaBianca

Cathryn Jeanne Christiansen

Tuan Anh Vo

Sagarika Mukesh

Sylvie M Mignot

Devika Sarkar Grant

Theodorus E Standaert

Chanro Park

Rudy J Wojtecki

Thomas M Shaw

Xiao Hu Liu

Deborah A Neumayer

Dario Leonardo Goldfarb

Vishnubhai Vitthalbhai Patel

Darryl D Restaino

Ranee W Kwong

Stephan Alan Cohen

Kelly Malone

Matthew S Angyal

Johnny Widodo

Huy Cao

Jae-hak Kim

Thamarai Selvi Devarajan

Prasad Bhosale

Steven E Molis

Nikhil Jain

Mary Claire Silvestre

Noel Arellano

Devika Sil

Ritwik Bhatia

Benjamin D Briggs

Shravan Kumar Matham

Han You

Chi-Chao Yang

Aakrati Jain

Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a first power plane electrically connected to a first plurality of via-to-backside power planes (VBPPs), a second power plane, and a plurality of pass through vias electrically connecting the second power plane to a second plurality of VBPPs, wherein the plurality of pass through vias pass through the first power plane.

Backside power plane

A semiconductor interconnect structure comprises a substrate, a plurality of metal lines disposed relative to the substrate and a plurality of first and second caps disposed on the metal lines wherein the first caps comprise a first dielectric material and the second caps comprise a second dielectric material different from the first dielectric material.

Dielectric caps for power and signal line routing

A back-end-of-line (BEOL) component includes a substrate and a first layer of dielectric material arranged on the substrate. The first layer of dielectric material includes openings. The BEOL component further includes a first layer of metal material arranged in the openings. The BEOL component further includes an etch stop layer arranged on top of the first layer of dielectric material. The BEOL component further includes a second layer of metal material in direct contact with the first layer of metal material. The second layer of metal material includes at least one projection extending above the etch stop layer. The BEOL component further includes a second layer of dielectric material arranged on top of the etch stop layer and surrounding the at least one projection.

Multilayer dielectric stack for damascene top-via integration

Bottom barrier free interconnects are provided. In one aspect, an interconnect structure includes: metal lines embedded in a dielectric; an interlayer dielectric (ILD) disposed over the metal lines; interconnects formed in the ILD on top of the metal lines; a barrier layer separating the interconnects from the ILD, wherein the barrier layer is absent in between the interconnects and the metal lines; and a selective capping layer disposed on the interconnects.

Bottom barrier free interconnects without voids

A semiconductor structure comprising a substrate, a first metal layer on top of the substrate, a second metal layer on top of the first metal layer and a dielectric layer adjacent to the second metal layer and at least part of the first metal layer and on top of at least part of the first metal layer. The first metal layer includes a via. The width of the second metal layer is the same as the width of the via of the first metal layer.

Top via patterning using metal as hard mask and via conductor

A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

Selective ILD deposition for fully aligned via with airgap

A semiconductor component includes an area of dielectric material extending below an uppermost surface of a substrate. The semiconductor component further includes a trench formed so as to extend from above the uppermost surface of the substrate into the area of dielectric material. The semiconductor component further includes a non-metal liner coating interior surfaces of the trench. The semiconductor component further includes a metal liner coating interior surfaces of the non-metal liner. The semiconductor component further includes a power rail formed in the trench in direct contact with at least one of the metal liner or the non-metal liner such that the power rail extends into the area of dielectric material and above the uppermost surface of the substrate.

High aspect ratio buried power rail metallization

Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

Method of forming copper interconnect structure with manganese barrier layer

A semiconductor structure with one or more backside metal layers that include a plurality of portions of a floating metal layer separated by dielectric material from one or more power and ground lines in the backside metal layer. The height of each of the plurality of portions of the floating metal layer in each of the one or more backside metal layers and the distance between adjacent portions of the plurality of portions of the floating metal layer in each of the one or more backside metal layer correlates to the capacitance of each of the one or more backside metal layers.

Backside floating metal for increased capacitance

A method of fabricating a dielectric film includes depositing a first precursor on a substrate. The first precursor includes a cyclic carbosiloxane group comprising a six-membered ring. The method also includes depositing a second precursor on the substrate. The first precursor and the second precursor form a preliminary film on the substrate, and the second precursor includes silicon, carbon, and hydrogen. The method further includes exposing the preliminary film to energy from an energy source to form a porous dielectric film.

Forming high carbon content flowable dielectric film with low processing damage

A method for fabricating a semiconductor device includes forming one or more layers including at least one of a liner and a barrier along surfaces of a first interlevel dielectric (ILD) layer within a trench, after forming the one or more liners, performing a via etch to form a via opening exposing a first conductive line corresponding to a first metallization level, and forming, within the via opening and on the first conductive line, a barrier-less prefilled via including first conductive material.

Barrier-less prefilled via formation

A semiconductor structure and a method for managing semiconductor wafer stress are disclosed. The semiconductor structure includes a semiconductor wafer, a first stress layer disposed on and in contact with a backside of the semiconductor wafer, and a second stress layer on and in contact with the first stress layer. The first stress layer exerts a first stress on the semiconductor wafer and the second layer exerts a second stress on the semiconductor wafer that is opposite the first backside stress. The method includes forming a first stress layer on and in contact with a backside of a semiconductor wafer, and further forming a second stress layer on and in contact with the first stress layer. The first stress layer exerts a first stress on the semiconductor wafer and the second stress layer exerts a second stress on the semiconductor wafer that is opposite to the first stress.

Wafer backside engineering for wafer stress control

A method for fabricating a semiconductor device including a skip via connection between metallization levels includes subtractively etching first conductive material to form a first via and a skip via on a first conductive line. The first via and the first conductive line are included within a first metallization level. The skip via is used to connect the first metallization level to a third metallization level above a second metallization level. The method further includes forming, on the first via from second conductive material, a second via disposed on a second conductive line. The second via and the second conductive line are included within the second metallization level.

Skip via connection between metallization levels

Copper interconnect structure with manganese barrier layer

Growing community of inventors

Armonk, NY, United States of America

Hosadurga K Shobha