International Business Machines Corporation

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Stmicroelectronics Gmbh

Samsung Electronics Co., Ltd.

Applied Materials, Inc.

Advanced Micro Devices Corporation

Chartered Semiconductor Manufacturing Ltd (corporation)

Adeia Semiconductor Solutions LLC

Hosadurga K Shobha

Son Van Nguyen

Lawrence Alfred Clevenger

Deepika Priyadarshini

Alfred Grill

Huai Huang

Daniel C Edelstein

Takeshi Nogami

Christopher J Penny

Benjamin David Briggs

Donald Francis Canaperi

Michael Rizzolo

Nicholas Anthony Lanzillo

Chih-Chao Yang

Thomas J Haigh, Jr

Yann Mignot

Sanjay C Mehta

Terry Allen Spooner

Fee Li Lie

Koichi Motoyama

Cornelius Brown Peethala

Matthew T Shoudy

Ruilong Xie

Junli Wang

Shom Ponoth

Ekmini Anuja De Silva

Vamsi Krishna Paruchuri

Gauri V Karve

Muthumanickam Sankarapandian

Yongan Xu

Raghuveer Reddy Patlolla

Joe Lee

E Todd Ryan

Seth L Knupp

Joshua L Herman

Sampath Purushothaman

Robert Russell Robison

Qinghuang Lin

Elbert Emin Huang

David Lee Rath

Indira P Seshadri

John Christopher Arnold

Nicole A Saulnier

Leigh Anne H Clevenger

Sagarika Mukesh

Isabel Cristina Chu

Devika Sarkar Grant

David V Horak

Ruqiang Bao

Hsueh-Chung Chen

Gareth Geoffrey Hougham

Chi-Chun Liu

Kisik Choi

Griselda Bonilla

Satyanarayana Venkata Nitta

Stephen L Buchwalter

Cheng Chi

Roger Allan Quon

Shyng-Tsong Chen

Kaushik Chanda

Claudius Feger

James John Kelly

Wei Wang

Wenhui Wang

Joseph F Maniscalco

Kenneth Chun Kuen Cheng

Nancy C LaBianca

Cathryn Jeanne Christiansen

Tuan Anh Vo

Sylvie M Mignot

Theodorus E Standaert

Chanro Park

Baozhen Li

Rudy J Wojtecki

Thomas M Shaw

Xiao Hu Liu

Deborah A Neumayer

Dario Leonardo Goldfarb

Vishnubhai Vitthalbhai Patel

Darryl D Restaino

Ranee W Kwong

Stephan Alan Cohen

Kelly Malone

Matthew S Angyal

Johnny Widodo

Huy Cao

Jae-hak Kim

Thamarai Selvi Devarajan

Prasad Bhosale

Steven E Molis

Nikhil Jain

Mary Claire Silvestre

Noel Arellano

Devika Sil

Ritwik Bhatia

Benjamin D Briggs

Shravan Kumar Matham

Han You

Aakrati Jain

A dual structure buried rail includes an upper rail and a lower rail. The upper rail may be inset relative to the lower rail. In other words, the lower rail may be wider than the upper rail, and/or the lower rail may have a larger geometrical volume than the upper rail. The upper rail may be located at a boundary of, and/or directly next to, an active device region and the lower rail may extend directly underneath at least a portion of the active device region. The lower rail may extend the entire length of the upper rail. The dual structure buried rail may reduce buried rail resistance which may reduce voltage drop thereacross and provide for improved semiconductor device and/or active device region performance. The dual structure buried rail may provide power potential delivery, provide potential sinking, or the like, to one or more active device region(s).

Dual structured buried rail

A skip-level through-silicon via structure is provided that enables low resistance via connection for backside power distribution by skipping one or more intermediate backside metal layers. The skip-level through-silicon via structure can enable a greater design flexibility for power grid. The skip-level through-silicon via structure has a large size that provides lower through-silicon via resistance as compared with conventional through-silicon via structures.

Skip-level TSV with hybrid dielectric scheme for backside power delivery

One or more systems, devices and/or methods provided herein relate to a circuit device having a modular or selectively designed interconnect structure with a plurality of conformal features. In the semiconductor realm, such achievements can allow for fabrication of a device with sub 18 nanometer (nm) or lesser pitch between adjacent and/or parallel lines of the interconnect structure. A device can comprise a semiconductor device having an interconnect structure having a first set of parallel lines and a second set of parallel lines, where the lines of the first set can be arranged in a transverse direction to the lines of the second set. The lines of the first set can be disposed orthogonally to the lines of the second set. The first second sets of lines can comprise first and second rounded jogs that are conformal to one another and which connect the first set of lines to the second set of lines.

Circuit interconnect structure

A semiconductor device includes a backside power rail, a backside ground rail, and a backside isolation rail between the backside power rail and the backside ground rail. The backside isolation rail may provide adequate electrical isolation between the backside power rail and the backside ground rail, thereby enabling the backside power rail and the backside ground rail to be located relatively near to one another. The backside isolation rail may also cure actual electrical shorts between the backside power rail and the backside ground rail.

Isolation rail between backside power rails

Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a first power plane electrically connected to a first plurality of via-to-backside power planes (VBPPs), a second power plane, and a plurality of pass through vias electrically connecting the second power plane to a second plurality of VBPPs, wherein the plurality of pass through vias pass through the first power plane.

Backside power plane

A semiconductor interconnect structure comprises a substrate, a plurality of metal lines disposed relative to the substrate and a plurality of first and second caps disposed on the metal lines wherein the first caps comprise a first dielectric material and the second caps comprise a second dielectric material different from the first dielectric material.

Dielectric caps for power and signal line routing

A back-end-of-line (BEOL) component includes a substrate and a first layer of dielectric material arranged on the substrate. The first layer of dielectric material includes openings. The BEOL component further includes a first layer of metal material arranged in the openings. The BEOL component further includes an etch stop layer arranged on top of the first layer of dielectric material. The BEOL component further includes a second layer of metal material in direct contact with the first layer of metal material. The second layer of metal material includes at least one projection extending above the etch stop layer. The BEOL component further includes a second layer of dielectric material arranged on top of the etch stop layer and surrounding the at least one projection.

Multilayer dielectric stack for damascene top-via integration

Bottom barrier free interconnects are provided. In one aspect, an interconnect structure includes: metal lines embedded in a dielectric; an interlayer dielectric (ILD) disposed over the metal lines; interconnects formed in the ILD on top of the metal lines; a barrier layer separating the interconnects from the ILD, wherein the barrier layer is absent in between the interconnects and the metal lines; and a selective capping layer disposed on the interconnects.

Bottom barrier free interconnects without voids

A semiconductor structure comprising a substrate, a first metal layer on top of the substrate, a second metal layer on top of the first metal layer and a dielectric layer adjacent to the second metal layer and at least part of the first metal layer and on top of at least part of the first metal layer. The first metal layer includes a via. The width of the second metal layer is the same as the width of the via of the first metal layer.

Top via patterning using metal as hard mask and via conductor

A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

Selective ILD deposition for fully aligned via with airgap

A semiconductor component includes an area of dielectric material extending below an uppermost surface of a substrate. The semiconductor component further includes a trench formed so as to extend from above the uppermost surface of the substrate into the area of dielectric material. The semiconductor component further includes a non-metal liner coating interior surfaces of the trench. The semiconductor component further includes a metal liner coating interior surfaces of the non-metal liner. The semiconductor component further includes a power rail formed in the trench in direct contact with at least one of the metal liner or the non-metal liner such that the power rail extends into the area of dielectric material and above the uppermost surface of the substrate.

High aspect ratio buried power rail metallization

Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

Method of forming copper interconnect structure with manganese barrier layer

A semiconductor structure with one or more backside metal layers that include a plurality of portions of a floating metal layer separated by dielectric material from one or more power and ground lines in the backside metal layer. The height of each of the plurality of portions of the floating metal layer in each of the one or more backside metal layers and the distance between adjacent portions of the plurality of portions of the floating metal layer in each of the one or more backside metal layer correlates to the capacitance of each of the one or more backside metal layers.

Backside floating metal for increased capacitance

A method of fabricating a dielectric film includes depositing a first precursor on a substrate. The first precursor includes a cyclic carbosiloxane group comprising a six-membered ring. The method also includes depositing a second precursor on the substrate. The first precursor and the second precursor form a preliminary film on the substrate, and the second precursor includes silicon, carbon, and hydrogen. The method further includes exposing the preliminary film to energy from an energy source to form a porous dielectric film.

Forming high carbon content flowable dielectric film with low processing damage

Growing community of inventors

Armonk, NY, United States of America

Hosadurga K Shobha