United Microelectronics Corp.

Horng-Nan Chern

Kun-Chi Lin

Kevin Lin

Tzung-Han Lee

Tri-Rung Yew

Chuan-Fu Wang

Tony Lin

Kuo-Tai Huang

Wen-Yi Hsieh

Hua-Chou Tseng

Chin-Sheng Yang

Chih-hsun Chu

Ming-Shing Chen

Wei-Ting Wu

Ming-Hui Chang

Alex Hou

Chorng-Lih Young

Kuen-Yow Lin

Hsi-Chia Lin

Ying-Chou Lai

Provided is a semiconductor device including a P-type substrate, a P-type first well region, an N-type second well region, a gate, N-type source and drain regions, a dummy gate and an N-type deep well region. The first well region is in the substrate. The second well region is in the substrate proximate to the first well region. The gate is on the substrate and covers a portion of the first well region and a portion of the second well region. The source region is in the first well region at one side of the gate. The drain region is in the second well region at another side of the gate. The dummy gate is on the substrate between the gate and the drain region. The deep well region is in the substrate and surrounds the first and second well regions. An operation method of the semiconductor device is further provided.

Semiconductor device and operating method thereof

The semiconductor wafer includes a substrate, a gate positioned on the substrate, a cap layer positioned on top of the gate, and a silicon oxide spacer positioned around both the gate and the cap layer. Firstly, a dielectric layer is formed on the semiconductor wafer to cover the gate. An etching back process is then performed to remove portions of both the dielectric layer and the silicon oxide spacer. Finally, a silicon nitride spacer is formed on the dielectric layer around the cap layer. The silicon nitride spacer is positioned on the surface of the dielectric layer and functions in reducing stress between the silicon nitride spacer and the substrate.

Method of reducing stress between a nitride silicon spacer and a substrate

A method for manufacturing the lower electrode of a DRAM capacitor. The method includes depositing polysilicon instead of amorphous silicon to form the lower electrode. Because polysilicon has a higher depositing temperature, it has a higher depositing rate capable of shortening depositing time. After forming the polysilicon lower electrode, the upper portion of the polysilicon layer is transformed into an amorphous layer by bombarding the polysilicon layer with ions to damage its internal structure. Eventually, hemispherical grain silicon is able to grow over the lower electrode, thereby increasing its surface area.

Method for manufacturing lower electrode of DRAM capacitor

A method of fabricating a wide-based boxed-structured capacitor containing hemi-spherical silicon grains. A substrate is provided with a source/drain and a first dielectric layer is formed on the substrate with a node contact opening. Then a doped polysilicon layer and a doped amorphous silicon layer are formed sequentially on the first dielectric layer. An etching step is performed to etch the doped amorphous silicon layer and the doped polysilicon layer and a wide-based lower electrode is formed by adjusting flow speeds of chlorine and of hydrogen bromide. Hemi-spherical silicon grains are formed on the surface of the doped amorphous silicon layer in the lower electrode. A second dielectric layer and an upper electrode are formed sequentially on the lower electrode and the capacitor is completed.

Method of fabricating a wide-based box-structured capacitor containing hemi-spherical grains

A method for forming a semiconductor dielectric layer comprising the steps of providing a substrate having a plurality of semiconductor devices already formed thereon, and then forming a first dielectric layer over the substrate. Next, a silicon oxy-nitride layer is formed over the first dielectric layer, and finally a second dielectric layer is formed over the silicon oxy-nitride layer.

Method for forming semiconductor dielectric layer

A process of fabricating a bottom electrode for the storage capacitors of DRAM is disclosed. The process includes first forming an insulation layer on the surface of the device substrate, with the insulation layer patterned to form a contact opening that exposes a source/drain region of the memory cell transistor. A first conductive layer then covers the insulation layer and fills into the contact opening, with the first conductive layer contacting the exposed source/drain region. A native oxide layer is then formed on the surface of the first conductive layer. A second electrically conductive layer is then formed and patterned to form a recess substantially above the location of the contact opening in the insulation layer. A layer of HSG&mdash;Si then covers the surface of the second conductive layer and the surface of the recess, and the HSG&mdash;Si layer and the second conductive layer are patterned to form the bottom electrode of the capacitor. The recess and its covering HSG&mdash;Si layer increase the effective surface area of the bottom electrode of the capacitor.

Method of forming DRAM capacitors with a native oxide etch-stop

A method of forming a borderless contact is described. An ion implantation process and a thermal process are performed on a device isolation structure to form a silicon nitride layer therein. During a process of forming a borderless contact window, the silicon nitride layer can serve as an etching stop layer to protect the device isolation structure from overetching. As a result, no recess is formed, and leakage current is avoided.

Method for forming a borderless contact

A method for forming a semiconductor device with avoiding chemical mechanical polishing caused residue on uncompleted fields of wafer edge is disclosed. The method comprising removing all conductive layers and silicon nitride layers on the uncompleted fields, thereby the height of the uncompleted fields will not higher than the height of the semiconductor device.

Method of avoiding CMP caused residue on wafer edge uncompleted field

A method for forming a capacitor of memory cell is disclosed. The method includes, firstly, there is a semiconductor substrate that owns a first dielectric layer formed thereon. The first dielectric layer has a contact opening filled with doped polysilicon to form a stud. Then, a second dielectric layer is formed on the first dielectric layer and the surface of the stud. A silicon oxynitride (SiON) layer can be formed on the second dielectric layer. A photoresist layer is formed on the silicon oxynitride layer. Portions of the silicon oxynitride layer and the second dielectric layer are etched. Blanket and conformably forming an amorphous silicon layer is carried out. A third dielectric layer is formed on the amorphous silicon layer. The third dielectric layer and a portion of the amorphous silicon layer atop of the silicon oxynitride layer are all etched back. The silicon oxynitride layer is used as an anti-etching layer. The amorphous silicon layer will be treated to form a hemispherical-grained (HSG) layer on the surface of the amorphous silicon layer. The silicon oxynitride layer is removed. Dipping the surface of the second dielectric layer is achieved to comprehensively clean the surface thereof, thereby preventing unwanted connection of the hemispherical-grained layer on the capacitor with the hemispherical-grained layer out of the capacitor.

Method for forming capacitor of memory cell

A method for depositing an oxide layer after spacer formation is disclosed. Owing to an oxide layer after spacer formation, therefore substantially increasing the effective thickness of spacer of the peripheral circuit. The method includes which includes a substrate on which an interior and a peripheral circuit are defined, wherein there is a gate oxide layer formed on the substrate. Sequentially an interior gate and a peripheral gate are formed. Then, N-type ions are implanted into the substrate of the interior and peripheral circuit. Consequently, conformal a second dielectric layer and a third dielectric layer are deposited above the substrate, interior gate, and peripheral gate, wherein second dielectric layer is etched to form a spacer of the interior gate and the peripheral gate. And then N.sup.+ -type ions are implanted into the substrate to form source/drain by using the peripheral gate, the spacer and a portion of the third dielectric layer that runs along the spacer as a mask. Subsequently, a blanket inter-plasma dielectric is deposited above the substrate. Finally, inter-polysilicon dielectric of the interior and peripheral circuit is etched anisotropically to form a plurality of contacts.

Method for increasing the effective spacer width

A method for fabricating a double-cylinder capacitor is provided. The double-cylinder capacitor has a storage electrode having dual, concentric cylinder structures. The dielectric layer and the top electrode are formed in sequence over the bottom electrode. The storage area is thus enlarged by the double-cylinder capacitor of the invention. Thus, the capacitance of the capacitor can be effectively increased.

Method of fabricating double-cylinder capacitor

A method for forming a hemispherical silicon grain (HSG) layer on a polysilicon electrode is provided. The method is suitable for a substrate, which has a dielectric layer over the substrate with an opening to expose the substrate, and a polysilicon layer is formed over the substrate. A portion of the polysilicon layer is removed above dielectric layer other than the opening region. Each sidewall of the polysilicon layer is slanted so that a trapezoidal polysilicon base is formed. A buffer layer is formed over the trapezoidal polysilicon base. An ion implantation process is performed to form an amorphous silicon layer with sufficient depth on a top surface region of the trapezoidal polysilicon base. The buffer layer includes silicon oxide or silicon nitride. During ion implantation, oxygen or nitrogen elements can also be bombarded into the amorphous silicon layer so as to buffer the amorphous silicon layer to be re-crystallized. A selective HSG layer is formed on the trapezoidal polysilicon electrode base.

Method for fabricating a hemispherical silicon grain layer

A method of manufacturing an alignment mark. A substrate having a device region and an alignment mark region is provided. The device region is higher than the alignment mark region. The device region comprises an active region. An isolation structure is formed in the substrate at the edge of the alignment mark region and a first dielectric layer is formed over a portion of the substrate at the alignment mark region, simultaneously. A conductive layer is formed over the substrate. A portion of the conductive layer is removed to expose the first dielectric layer at the alignment mark region. The remaining conductive layer is patterned to form a component at the active region. A second dielectric layer with a smooth surface is formed over the substrate to cover the component. A wire is formed on the second dielectric layer, wherein a distance between the wire and the alignment mark region is larger than a distance between the component and the alignment mark region.

Method of manufacturing an alignment mark with an etched back dielectric

A fabricating method and a structure of a stacked-type capacitor is provided comprising forming a first dielectric layer having a first via on a semiconductor substrate. A first conductive layer is filled into the first via. Then, insulating layers and dielectric layers are formed. A photolithography step is used to form a second dendriform via in the insulating layers and the dielectric layers. A second conductive layer is filled in the second dendriform via. The insulating layers and conductive layers are removed to form a dendriform lower electrode. The dendriform electrode provides a larger surface area to increase capacitance. Further, a polysilicon layer of hemispherical grains is formed to increase the surface area of the lower electrode.

Fabricating method of stacked type capacitor

The method in the present invention for forming insulation over conductor includes the following steps. At first, a substrate with a first conductor formed over is provided. The first conductor can be either a gate structure or an interconnection layer. A dielectric layer is then formed over the first conductor the substrate. A portion of the dielectric layer is removed for having a recess free sidewall on the dielectric layer around the first conductor. An insulation for succeeding conductive layer is formed.

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Tainan Hsien, Taiwan

Horng-Nan Chern