Taiwan Semiconductor Manufacturing Comp. Ltd.

Vanguard International Semiconductor Corporation

Industrial Technology Research Institute

Other

Mass International Co., Ltd.

Vanguard Int'l Semiconductor Corp.

Horng-Huei Tseng

Che-Cheng Chang

Chih-Han Lin

Chi-Wen Liu

Chih-Yuan Lu

Chenming Hu

Yu-Cheng Liu

Hung-Hao Chen

Wen-Tung Chen

Yu-Hung Lin

Po-Chi Wu

Chao-Hsiung Wang

Chen-Hua Douglas Yu

Kuo-Cheng Lee

Yun-Wei Cheng

Chun-Hao Chou

Hsin-Chieh Huang

Yung-Lung Hsu

Tsung-Han Tsai

Yirn-Sheng Pan

Syun-Ming Jang Jang

Yi-Jen Chen

Jie-Cheng Deng

Chang-Yin Chen

Denny Tang

David Lu

Da-Chi Lin

Shiu-Ko JangJian

Chi-Cheng Hung

Kuo-Ching Chiang

Sin-Yi Yang

Yen-Ming Peng

Kai-Yu Cheng

Yi-Ju Hsu

Chin-Hsiang Lin

Chi-Ming Yang

Tsung-Yu Chiang

Burn-Jeng Lin

Jyh-Chyurn Guo

Cheng-Chien Huang

Chun-Yen Kuo

Chie-Wun Chiou

Jeng-Tyan Lin

Jhy-Chyum Guo

Chung-Shi Liu

Ching-Yu Chang

Ru-Gun Liu

Shau-Lin Shue

Yee-Chia Yeo

Kei-Wei Chen

Fu-Liang Yang

Ying-Lang Wang

Tsai-Sheng Gau

Tzu-Hsuan Hsu

Chun-Kuang Chen

Chih-Hao Chen

Chien-Hung Lin

Chien-Chao Huang

Wen-Chin Lin

Hung Jui Chang

Chung-Chieh Lee

Jen-Chieh Shih

Shu-Hao Huang

Te-Ming Kung

Ping-Kun Wu

Jeng-Jyi Hwang

Su-fen Lin

Chin-Yuan Lu

Jenq-Tyan Lin

Hung-Ming Hsieh

Yu-Li Hung

Mark Hsieh

Chine-Gie Lo

Huei-Wen Hsu

A semiconductor structure includes a first fin, a second fin, a first gate, a second gate, at least one spacer, and an insulating structure. The first gate is present on the first fin. The second gate is present on the second fin. The spacer is present on at least one side wall of at least one of the first gate and the second gate. The insulating structure is present between the first fin and the second fin, in which the spacer is substantially absent between the insulating structure and said at least one of the first gate and the second gate.

Semiconductor structure and manufacturing method thereof

An exemplary semiconductor device includes first spacers disposed along sidewalls of a first gate structure and second spacers disposed along sidewalls of a second gate structure. A source/drain region is disposed between the first gate structure and the second gate structure. A first ILD layer is disposed between the first spacers and the second spacers. A portion of the first ILD layer has a first recessed upper surface. A dielectric layer is disposed over the first spacers, the second spacers, and the first recessed upper surface of the first ILD layer. A portion of the dielectric layer has a second recessed upper surface that is disposed over the portion of the first ILD layer having the first recessed upper surface. A second ILD layer is disposed over the dielectric layer. A contact extends through the second ILD layer, the dielectric layer, and the first ILD layer to the source/drain region.

Enlarging spacer thickness by forming a dielectric layer over a recessed interlayer dielectric

A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively.

Removing polymer through treatment

A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.

FinFET device and method of forming and monitoring quality of the same

A FinFET including a gate stack, a semiconductor fin embedded in the gate stack, a source and a drain disposed is provided. The semiconductor fin extends along a widthwise direction of the gate stack and has a first concave and a second concave exposed at sidewalls of the gate stack respectively. The source and drain are disposed at two opposite sides of the gate stack. The source includes a first portion in contact with and embedded in the first concave. The drain includes a second portion in contact with and embedded in the second concave. The first portion and the second portion are covered by the gate stack.

Method for manufacturing FinFETs by fin-recessing processes to form v-shaped concaves and rounded concaves into gate stacks

A method includes forming a first active fin structure and a second active fin structure on a substrate. A dummy fin structure is formed on the substrate, the dummy fin structure being interposed between the first active fin structure and the second active fin structure. The dummy fin structure is removed to expose a first portion of the substrate, the first portion of the substrate being disposed directly below the dummy fin structure. A plurality of protruding features is formed on the first portion of the substrate. A shallow trench isolation (STI) region is formed over the first portion of the substrate, the STI region covering the plurality of protruding features, at least a portion of the first active fin structure and at least a portion of the second active fin structure extending above a topmost surface of the STI region.

FinFET device comprising plurality of dummy protruding features

An integrated circuit includes a substrate, at least one n-type semiconductor device, and at least one p-type semiconductor device. The n-type semiconductor device is present on the substrate. The n-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the n-type semiconductor device and the sidewall of the gate structure of the n-type semiconductor device intersect to form an interior angle. The p-type semiconductor device is present on the substrate. The p-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the p-type semiconductor device and the sidewall of the gate structure of the p-type semiconductor device intersect to form an interior angle smaller than the interior angle of the gate structure of the n-type semiconductor device.

Integrated circuit and manufacturing method thereof

A semiconductor device and method of manufacture are provided. A source/drain region is formed next to a spacer, which is adjacent to a gate electrode. An implantation is performed through an implantation mask into the source/drain region as well as the first spacer, forming an implantation region within the spacer.

Semiconductor device and method

A method includes, in a first etching step, etching a semiconductor substrate to form first recesses in a first device region and second recesses in a second device regions simultaneously. A first semiconductor strip is formed between the first recesses. A second semiconductor strip is formed between the second recesses. In a second etching step, the semiconductor substrate in the second device region is etched to extend the second recesses. The first recesses and the second recesses are filled with a dielectric material to form first and second isolation regions in the first and second recesses, respectively. The first isolation regions and the second isolation regions are recessed. Portions of the semiconductor substrate in the first and the second device regions protrude higher than top surfaces of the respective first and second isolation regions to form a first and a second semiconductor fin, respectively.

Fin structure and method of forming same through two-step etching processes

A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of forming a gate structure having a first lateral width, and forming a first via opening over the gate structure. The first via opening has a lowermost portion that exposes an uppermost surface of the gate structure. The lowermost portion of the first via opening has a second lateral width. A ratio of the second lateral width to the first lateral width is less than about 1.1. A source/drain (S/D) region is disposed laterally adjacent the gate structure. A contact feature is disposed over the S/D region. A second via opening extends to and exposes an uppermost surface of the contact feature. A bottommost portion of the second via opening is disposed above a topmost portion of the gate structure.

Semiconductor device having a conductive contact in direct contact with an upper surface and a sidewall of a gate metal layer

An embodiment method includes forming first dummy gate stack and a second dummy gate stack over a semiconductor fin. A portion of the semiconductor fin is exposed by an opening between the first dummy gate stack and the second dummy gate stack. The method further includes etching the portion of the semiconductor fin to extend the opening into the semiconductor fin. A material of the semiconductor fin encircles the opening in a top-down view of the semiconductor fin. The method further includes epitaxially growing a source/drain region in the opening on the portion of the semiconductor fin.

Source/drain regions in fin field effect transistors (FinFETs) and methods of forming same

A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.

Semiconductor device and method of manufacture

A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions is present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of an interconnection structure in the semiconductor device is reduced.

Interconnection structure, fabricating method thereof, and semiconductor device using the same

A back side illumination (BSI) image sensor with a dielectric grid opening having a planar lower surface is provided. A pixel sensor is arranged within a semiconductor substrate. A metallic grid is arranged over the pixel sensor and defines a sidewall of a metallic grid opening. A dielectric grid is arranged over the metallic grid and defines a sidewall of the dielectric grid opening. A capping layer is arranged over the metallic grid, and defines the planar lower surface of the dielectric grid opening.

Stacked grid design for improved optical performance and isolation

A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the first dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

Semiconductor device

Growing community of inventors

Hsinchu, Taiwan

Horng-Huei Tseng