United Microelectronics Corp.

Horng-Bor Lu

Kun-Lin Wu

Jenn-Tarng Lin

Ing-Tang Chen

Chi-Rong Lin

I T Chen

Clint Wu

Wen-Yi Hsieh

Yu-Ru Yang

Yi-Ching Wu

Ellis Lee

Hao-Kuang Chiu

Yung-Chieh Kuo

Kuen-Jian Chen

Ru-Huei Chang

Chen-Nan Huang

Hao-Kuang Shiu

Chien-Hsien Lai

Jyh-J Huang

Chi-Jung Lin

A method for planarizing a semiconductor device is provided. The method includes steps hereinafter. A substrate is provided with a first dielectric layer covering at least one electrode structure formed thereon. A chemical-mechanical polishing (CMP) process is performed on the first dielectric layer until the at least one electrode structure is exposed. A second dielectric layer is deposited covering the at least one electrode structure and the first dielectric layer. An etching-back process is performed on the second dielectric layer until the at least one electrode structure is exposed.

Method for planarizing semiconductor device

Structures for reducing relative stress between HDP layer and passivation layer are proposed by the invention, where the HDP layer is formed by high density plasma and the passivation layer is a conventional passivation layer. The invention provides some structures that can be divided into two categories: one, a low stress passivation layer is directly formed on a HDP layer; another, a low stress layer is formed between passivation layer and HDP layer to reduce relative layer that between any two adjacent layers. Therefore, it is crystal-clear that possible structures of the invention comprise following varieties: First, a low stress passivation layer is located between a passivation layer and a HDP layer. Second, a lower stress passivation layer directly locates on a HDP layer. Third, a low stress layer is formed between a passivation layer and a HDP layer.

Reducing relative stress between HDP layer and passivation layer

A method to treat a silicon oxynitride surface, including a silicon oxynitride surface covered by a photo resist layer, is described in which the photo resist layer is first removed by an oxygen plasma treatment process, followed by an argon plasma treatment process to overetch the SiON layer.

Treatment on silicon oxynitride

A semiconductor wafer includes a substrate, an aluminum layer on the substrate, an anti-reflection coating on the aluminum layer, a dielectric layer on the anti-reflection coating, and a via hole that passes through the dielectric layer and the anti-reflection coating down to a predetermined depth within the aluminum layer. A titanium layer is formed on the bottom and on the walls of the via hole. A physical vapor deposition process is then performed to form a first titanium nitride layer on the titanium layer. A chemical vapor deposition process is then performed to form a second titanium nitride layer on the first titanium nitride layer.

Method for preventing aluminum intrusions

A deposition process for forming a void-free dielectric layer is described. A first dielectric layer,is formed over a conductor pattern,A second dielectric layer,is formed to conform to the first dielectric layer. A third dielectric layer,is formed to cover the second dielectric layer. The first, second, and third dielectric layers can be formed by high density plasma deposition, atmospheric pressure deposition, and plasma enhanced deposition, respectively. The second dielectric layer can alternatively be formed by plasma enhanced deposition.

Deposition process for forming void-free dielectric layer

A method for preventing the occurrence of poisoned trenches and vias in a dual damascene process that includes performing a densification process, such as an implantation process, on the surface of the exposed dielectric layer around the openings before the openings are filled with conductive material. The densified surface of the dielectric layer is able to efficiently prevent the occurrence of poisoned trenches and vias caused by the outgassing phenomena.

Method for preventing poisoned vias and trenches

A method for fabricating a shallow trench isolation in a semiconductor substrate. A mask layer is formed on the substrate. The mask layer is patterned and used as a mask in order to form a trench in the substrate. A portion of the substrate is removed to form the trench in the substrate. A liner layer is formed on the substrate exposed by the trench and optionally, an additonal liner layer is formed on the liner layer. A doped isolation layer is formed to fill the trench. A densification step is performed. The mask layer is removed. The doped isolation layer has a lower glass transition temperature so that the temperature of the densification step is reduced to about 700&deg; C. to 1000&deg; C.

Method of fabricating shallow trench isolation

A method for forming a metal plug is provided. The method is used to form a metal plug without a hole on a glue/barrier layer within a trench when the glue/barrier layer has been formed for a while. A substrate with a trench therein and a glue/barrier layer formed conformal to the profile of the substrate is provided. A post-treatment is performed on the glue/barrier layer to prevent moisture absorption and to make the glue/barrier become dense. The post-treatment comprises a plasma treatment or a deep UV plus laser treatment. After performing the post-treatment step, a metal layer is formed on the glue/barrier layer at least to fill in the trench. The metal layer other than that filling the trench is removed to form a metal plug.

Method for forming a metal plug

A method for forming a barrier/glue layer above the polysilicon layer of a MOS transistor gate comprising the step of providing a semiconductor substrate, and then forming a gate oxide layer above the substrate. Next, a polysilicon layer is formed over the gate oxide layer. Thereafter, a titanium layer is deposited over the polysilicon layer first, and then a titanium nitride layer is deposited above the titanium layer. This titanium/titanium nitride bi-layer is capable of increasing the adhesive strength with a subsequently deposited tungsten silicide layer, and preventing the peeling of the tungsten silicide layer. Furthermore, the titanium nitride layer acts as a barrier for fluorine atoms preventing their diffusion to the gate oxide layer/polysilicon layer interface, and affecting the effective thickness of the gate oxide layer. In the subsequent step, a tungsten suicide layer is formed above the titanium nitride layer. Finally, after an annealing operation, the titanium layer will react with the silicon in the polysilicon layer and the tungsten silicide layer to form a titanium silicide layer. Hence, the resistance of the polycide layer in a MOS transistor gate can be reduced.

Barrier/glue layer on polysilicon layer

An apparatus for detecting the position of a collimator in a sputter-processing chamber is disclosed in the present invention. A target holder is at the upper portion of the chamber and a target is attached to the bottom surface of the target holder. A substrate holder is at the underlying portion of the chamber and it is opposed to the target holder. A silicon wafer is putted on the substrate holder. Two supporters are on an inner surface of the housing of the chamber and are separated to oppose to each other, the supporters protrude the housing. A collimator is putted on the supporters and it is parallel to the surface of the target. Two sensors is attached on the under surface or the lateral surface of the supporters. The horizontal height of the sensors is lower than that of the collimator. When the collimator is heated and it distorts, the position of the collimator will change to enter into the available area of the sensors. Afterwards, an alarm will announce a notice to supervisors of the sputtering system.

Apparatus for detecting position of collimator in sputtering processing

A gas delivering apparatus useful for improving the level of uniformity of thin film deposited over a silicon wafer in a chemical vapor deposition. By reshaping the injector from a conventional straight hollow tube to a funnel-shaped profile, the opening of the injector is widened. With a wider injector opening, the gas flow rate becomes slower and hence more capable of spreading over a wider wafer surface area. Consequently, a uniform gas flow pattern is established resulting in the deposition of a uniform layer.

Gas delivering apparatus for chemical vapor deposition

A method for reducing the stress on a titanium nitride layer formed by collimator sputtering. On a semiconductor substrate, an insulated oxide layer is formed. A trench is formed in the insulated oxide layer. On the trench, a first titanium nitride layer is formed conformally by using physical or chemical vapor deposition as a buffer layer. A second titanium nitride layer is formed by collimator sputtering on the first titanium layer. The orientation of lattice arrangement of the second titanium nitride layers is changed from &lt;100&gt;-orientation to &lt;111&gt;-orientation, and therefore, the stress is reduced.

Method for reducing stress on collimator titanium nitride layer

The present invention provides a method of forming a dielectric layer on a semiconductor wafer. The semiconductor wafer comprises a bottom dielectric layer and a plurality of metal lines each having a rectangular cross section positioned on the bottom dielectric layer. The method is performed in a high-density plasma chemical vapor deposition apparatus. A first deposition process at a first etching/deposition (E/D) ratio is performed to form a first dielectric layer with a predetermined thickness on the semiconductor wafer. The first dielectric layer covers the surface of the metal lines and forms a triangular ridge above each metal line. The upper side of each of the ridges has two slanted side-walls. Then, a second deposition process at a second E/D ratio is performed to form a second dielectric layer with a predetermined thickness on the semiconductor wafer with the second deposition process etching rate being near zero. The second dielectric layer above each metal line reduces the slope of the two slanted side-walls of the ridges. Thus, a dielectric layer with the first dielectric layer and the second layer is formed.

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Hsinchu, Taiwan

Horng-Bor Lu