Samsung Electronics Co., Ltd.

Hoonjoo Na

Sangjin Hyun

Kwangjin Moon

Seokho Kim

Jaehyung Park

Jinnam Kim

Wonkeun Chung

Kyuha Lee

Dongsoo Lee

Joohee Jang

Jaeyeol Song

Hongbae Park

Suyoung Bae

Hye-Lan Lee

Hyungjun Jeon

HyungSuk Jung

Hyung-seok Hong

Hagju Cho

Jonghan Lee

Hoechul Kim

Yugyun Shin

Seongmin Son

Taeyeong Kim

Taeseong Kim

Sangyong Kim

Jae-Jung Kim

Hyung-Seok Hong

Jinkyu Jang

Sughun Hong

Yikoan Hong

Sunghun Hong

Sonkwan Hwang

Ju-Il Choi

Pil-Kyu Kang

Weonhong Kim

Hakseung Lee

Seungha Oh

Hyoukyung Cho

Pilkyu Kang

Eunsuk Jung

Wandon Kim

Kang-Ill Seo

Hyosan Lee

Hojin Lee

Siyoung Choi

Rakhwan Kim

Jun Hyung Kim

Hyeok-Jun Son

Kichul Park

Minsoo Han

KyoungWoo Lee

Chunghwan Shin

Anthony Dongick Lee

Sangcheol Na

Hakjun Lee

Yoonsuk Kim

Sohye Cho

Juyoung Jung

Jungseob So

Moonkyu Park

Jun-Woong Park

Jaehyun Phee

Hongkeun Park

Byungchul Kang

Eunji Jung

Doohwan Park

A semiconductor device includes a substrate. A wiring layer is over the substrate. A first via structure directly contacts a lower portion of the wiring layer. A second via structure directly contacts an upper portion of the wiring layer. The first via structure generates first stress in the wiring layer. The second via structure generates second stress in the wiring layer. The second stress is of an opposite type to the first stress. The first stress and the second stress compensate for each other in the wiring layer.

Semiconductor device including via structure

A semiconductor package includes a first structure including a first semiconductor chip comprising a first semiconductor integrated circuit, and a second structure on the first structure. The second structure includes a second semiconductor chip including a second semiconductor integrated circuit, a semiconductor pattern horizontally spaced apart from the second semiconductor chip and on a side surface of the second semiconductor chip, an insulating pattern between the second semiconductor chip and the semiconductor pattern, and through-electrode structures. At least one of the through-electrode structures penetrates through at least a portion of the second semiconductor chip or penetrates through the semiconductor pattern. The semiconductor pattern has a first side surface facing the side surface of the second semiconductor chip and a second side surface opposing the first side surface. The second side surface of the semiconductor pattern is vertically aligned with a side surface of the first semiconductor chip.

Semiconductor packages

A semiconductor device includes a substrate that includes an active pattern, a channel pattern and a source/drain pattern on the active pattern, a gate electrode on the channel pattern, an active contact electrically connected to the source/drain pattern, and a gate contact electrically connected to the gate electrode. The active contact includes a first barrier pattern, a first seed pattern on the first barrier pattern, a first fill pattern on the first seed pattern, and a first metal-containing pattern between the first seed pattern and the first fill pattern. The first metal-containing pattern includes tungsten nitride. A nitrogen concentration of the first metal-containing pattern decreases in a direction toward the substrate.

Semiconductor device

A semiconductor package includes first to fourth semiconductor chips sequentially stacked on one another. A backside of a third substrate of the third semiconductor chip may be arranged to face a backside surface of a second substrate of the second semiconductor chip such that the third substrate and a second backside insulation layer provided on the backside surface of the second substrate are bonded directly to each other, or the backside of the third substrate may be arranged to face a front surface of the second substrate such that the third substrate and a second front insulation layer provided on the front surface of the second substrate are bonded directly to each other.

Semiconductor packages and methods of manufacturing the semiconductor packages

The semiconductor device includes a lower chip structure including a peripheral circuit, a first memory chip structure on the lower chip structure, and a second memory chip structure on the first memory chip structure. The first memory chip structure includes a first stack structure and a first vertical memory structure. The first stack structure includes first gate lines stacked in a vertical direction and extending in a first horizontal direction. The first vertical memory structure penetrates through the first gate lines in the vertical direction. The second memory chip structure includes a second stack structure and a second vertical memory structure. The second stack structure includes second gate lines stacked in the vertical direction and extending in a second horizontal direction, perpendicular to the first horizontal direction. The second vertical memory structure penetrates through the second gate lines in the vertical direction.

Semiconductor device including a lower chip including a peripheral circuit and first and second memory chips vertically stacked thereon and data storage system including the same

A three-dimensional semiconductor device includes a first substrate; a plurality of first transistors on the first substrate; a second substrate on the plurality of first transistors; a plurality of second transistors on the second substrate; and an interconnection portion electrically connecting the plurality of first transistors and the plurality of second transistors. Each of the plurality of first transistors includes a first gate insulating film on the first substrate and having a first hydrogen content. Each of the plurality of second transistors includes a second gate insulating film on the second substrate and having a second hydrogen content. The second hydrogen content is greater than the first hydrogen content.

Three-dimensional semiconductor devices and method of manufacturing the same

A method includes forming a first substrate including a first dielectric layer and a first metal pad, forming a second substrate including a second dielectric layer and a second metal pad, and bonding the first dielectric layer to the second dielectric layer, and the first metal pad to the second metal pad. One or both of the first and second substrates is formed by forming a first insulating layer, forming an opening in the layer, forming a barrier on an inner surface of the opening, forming a metal pad material on the barrier, polishing the metal pad material to expose a portion of the barrier and to form a gap, expanding the gap, forming a second insulating layer to fill the opening and the gap, and polishing the insulating layers such that a top surface of the metal pad is substantially planar with an upper surface of the polished layer.

Semiconductor device and method of manufacturing the same

A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

Method of fabricating a semiconductor device

A semiconductor device including a semiconductor substrate, an integrated circuit layer on the semiconductor substrate, first to nmetal wiring layers (where n is a positive integer) sequentially stacked on the semiconductor substrate and the integrated circuit layer, a first through via structure extending in a vertical direction toward the semiconductor substrate from a first via connection metal wiring layer, which is one of the second to nmetal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate, and a second through via structure being apart from the first through via structure, extending in a vertical direction toward the semiconductor substrate from a second via connection metal wiring layer, which is one of the second to nmetal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate may be provided.

Semiconductor device including through via structure

Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.

A semiconductor package includes a first semiconductor chip, a second semiconductor chip, first main connection pad structures, and first dummy connection pad structures. The first main connection pad structures are arranged at an interface between the first semiconductor chip and the second semiconductor chip and arranged to be apart from each other by a first main pitch in a first direction parallel to a top surface of the first semiconductor chip, wherein each of the first main connection pad structures includes a first connection pad electrically connected to the first semiconductor chip, and a second connection pad electrically connected to the second semiconductor chip and contacting the first connection pad. The first dummy connection pad structures are arranged at an interface between the first semiconductor chip and the second semiconductor chip, are arranged to be apart from the first main connection pad structures, and are arranged to be apart from each other by a first dummy pitch in the first direction, the first dummy pitch being greater than the first main pitch.

A semiconductor package includes a first structure including a first semiconductor chip, and a second structure on the first structure. The second structure includes a second semiconductor chip, a semiconductor pattern horizontally spaced apart from the second semiconductor chip and on a side surface of the second semiconductor chip, an insulating gap fill pattern between the second semiconductor chip and the semiconductor pattern, and through-electrode structures. At least one of the through-electrode structures penetrates through at least a portion of the second semiconductor chip or penetrates through the semiconductor pattern.

A semiconductor device includes a first adsorption layer, a first bonding layer, a second bonding layer, and a second adsorption layer stacked on a first substrate, and a conductive pattern structure penetrating through the first adsorption layer, the first bonding layer, the second bonding layer and the second adsorption layer. The first and second bonding layers are in contact with each other, and each of the first and second adsorption layers includes a low-&#x3ba; dielectric material.

Method of manufacturing a semiconductor device including bonding layer and adsorption layer

Semiconductor packages stacked by wafer bonding process and methods of manufacturing the semiconductor packages

A semiconductor device includes a substrate having a first surface on which an active region is disposed, and a second surface opposite the first surface, a buried conductive line extending in one direction and having a portion buried in the active region, an insulating portion covering the buried conductive line, a contact structure disposed on the insulating portion and connected to the buried conductive line, a through-hole extending from the second surface to the insulating portion and exposing the buried portion of the buried conductive line, an insulating isolation film disposed on a side surface of the buried conductive line and exposing a bottom surface of the buried portion and a side surface adjacent to the bottom surface, a through-via contacting the bottom surface and the adjacent side surface of the buried conductive line, an insulating liner surrounding the through-via.

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Hwaseong-si, South Korea

Hoonjoo Na