Freescale Semiconductor,inc.

Nxp Usa, Inc.

Hongzhong Xu

Richard T Ida

Jiang-kai Zuo

Zhihong Zhang

James D Whitfield

Won Gi Min

Michael Baird

Sopan Joshi

Vijay Parthasarathy

Chai Ean Gill

Rouying Zhan

Chai Ean E Gill

Jinman Yang

Beth A Baumert

Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices, e.g., LDMOS transistors, by careful charge balancing, even when body and drift region charge balance is not ideal, by: (i) providing a plug or sinker near the drain and of the same conductivity type extending through the drift region at least into the underlying body region, and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall coupled to the device buried layer, and/or (iii) providing a variable resistance bridge between the isolation wall and the drift region. The bridge may be a FET whose source-drain couple the isolation wall and drift region and whose gate receives control voltage Vc, or a resistor whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer via the isolation wall.

Resurf semiconductor device charge balancing

RESURF semiconductor device charge balancing

A semiconductor device includes an isolated p-type well, wherein the isolated p-type well is a first electrode of a capacitor device; a capacitor dielectric on the isolated p-type well; a p-type polysilicon electrode over the capacitor dielectric, wherein the p-type polysilicon electrode is a second electrode of the capacitor device; a first p-type contact region in the isolated p-type well, laterally extending from a first sidewall of the p-type polysilicon electrode; a second p-type contact region in the isolated p-type well, laterally extending from a second sidewall of the p-type polysilicon electrode, opposite the first sidewall of the p-type polysilicon electrode, wherein a portion of the isolated p-type well between the first and second p-type contact regions is under the p-type polysilicon electrode and the capacitor dielectric; and an n-type isolation region surrounding the isolated p-type well. This device may be conveniently coupled to a fringe capacitor.

Capacitor device using an isolated well and method therefor

Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices (), e.g., LDMOS transistors, by careful charge balancing, even when body () and drift () region charge balance is not ideal, by: (i) providing a plug or sinker () near the drain () and of the same conductivity type extending through the drift region () at least into the underlying body region (), and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall () coupled to the device buried layer (), and/or (iii) providing a variable resistance bridge () between the isolation wall () and the drift region (). The bridge () may be a FET () whose source-drain () couple the isolation wall () and drift region () and whose gate () receives control voltage Vc, or a resistor () whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer () via the isolation wall ().

An electrostatic discharge (ESD) protection device () coupled across input-output (I/O) () and common () terminals of a core circuit () that it is intended to protect from ESD events, comprises, one or more serially coupled resistor triggered ESD clamp stages (&#x2033;), each stage (&#x2033;) comprising first (T, T', T&#x2033;, etc.) and second transistors (T, T&#x2032;, T&#x2032;&#x2033; etc.) having a common collector (&#x2033;) and first (&#x2033;) and second (&#x2033;) emitters providing terminals (&#x2033;) of each clamp stage (. A first emitter () of the first stage () couples to the common terminal () and a second emitter (&#x2033;) of the last stage (&#x2032;) couples to the I/O terminals (). Zener diode triggers are not used. Integrated external ESD trigger resistors (&#x2033;) (e.g., of poly SC) are coupled between the base (&#x2033;) and emitter (&#x2033;) of each transistor (T, T&#x2032;, T&#x2033;; T, T&#x2032;, T&#x2033;). Different resistor values (e.g., &#x2dc;0.5 k to 150 k Ohms) give different ESD trigger voltages. Cascading the clamp stages () gives even higher trigger voltages. The ESD trigger resistances (&#x2033;) are desirably located outside the common collector-isolation wall (&#x2033;) surrounding the transistors (T, T&#x2032;, T&#x2033;; T, T&#x2032;, T&#x2033;).

Resistor triggered electrostatic discharge protection

An electrostatic discharge (ESD) protection clamp () for I/O terminals () of integrated circuits (ICs) () comprises an NPN bipolar transistor () coupled to an integrated Zener diode (). Variations in the break-down current-voltage characteristics () of multiple prior art ESD clamps () in different parts of the same IC chip is avoided by forming the anode () of the Zener () in the shape of a base-coupled P+ annular ring () surrounded by a spaced-apart N+ annular collector ring () for the cathode () of the Zener (). Even though an angled implant () used to form the N+ annular collector ring () causes location dependent variations in the width () of the Zener space charge (ZSC) region (), the improved annular shaped clamp () always has a portion that initiates break-down at the design voltage so that variations in the width () of the ZSC region () do not cause significant variations in the clamp's current-voltage characteristics ().

Complementary zener triggered bipolar ESD protection

Methods and apparatus for ESD protection of LDMOS devices are provided. The apparatus comprises two LDMOS devices, with source, drain and gate contacts parallel coupled. One is the protected device and the other is the protecting device. Each has source region, drain region, gate, first body well region containing the source, second body well region containing the drain and separated from the first body well region by a drift region, an isolation region separated from the first and second body well regions and a buried layer contacting the isolation region. The protecting device has a further region of the same type as the drain, coupling the drain to the isolation region. Its drain connection is made via a contact to its isolation region rather than its drain region. The drift region of the protecting device is desirably smaller and the isolation-body well separation larger than for the protected device.

Process insensitive ESD protection device

Systems and methods are described for a low-voltage electrostatic discharge clamp. A resistor pwell-tied transistor may be used as a low-voltage ESD clamp, where the body of the transistor is coupled to the source by a resistor, thereby reducing a DC leakage current and minimizing latch-ups in the transistor while maintaining effective ESD performance.

Low voltage NMOS-based electrostatic discharge clamp

Methods and apparatus are provided an electrostatic discharge (ESD) protection device having a first terminal and a second terminal. The ESD protection device comprises a vertical transistor having a collector coupled to the first terminal, a base, and an emitter coupled to the second terminal. A zener diode has a first terminal coupled to the first terminal of the ESD protection device and a second terminal coupled to the base of the vertical transistor. Subsurface current paths are provided to redistribute current from a surface of the vertical transistor in an ESD event. The method comprises generating an ionization current when a zener diode breaks down during an ESD event. The ionization current density from a surface zener diode region is reduced. The ionization current enables a transistor to dissipate the ESD event.

Electrostatic discharge protection device and method therefore

A low voltage thyristor is disclosed that can be used to provide protection during electrostatic discharge event. The thyristor is connected between voltage reference nodes having a common potential, such as ground nodes, that are isolated from one another during normal operating conditions. During an ESD event on one of the voltage reference nodes, the low voltage thyrister triggers, at a voltage of less than ten volts, to help discharge the ESD current through the otherwise isolated ground node.

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Gilbert, AZ, United States of America

Hongzhong Xu