Sony Semiconductor Solutions Corporation

Hongyi Mi

Frederick T Brady

Pooria Mostafalu

Sungin Han

An imaging device includes a plurality of unit pixels disposed into pixel groups that are separated from one another by isolation structures. Unit pixels within each pixel group are separated from one another by isolation structures and share circuit elements. The isolation structures between pixel groups are full thickness isolation structures. At least a portion of the isolation structures between unit pixels within a pixel group are deep trench isolation structures.

Solid-state imaging device and imaging device with shared circuit elements

Binning in a hybrid pixel structure of image pixels and event vision sensor (EVS) pixels. In one embodiment, the imaging sensor includes a pixel array including a plurality of pixel circuits and a plurality of binning transistors. A first portion of the plurality of pixel circuits individually includes an intensity photodiode. A second portion of the plurality of pixel circuits individually includes an event vision sensor (EVS) photodiode. The plurality of binning transistors is configured to bin together at least one of the first portion or the second portion.

Binning in hybrid pixel structure of image pixels and event vision sensor (EVS) pixels

Image sensing devices are disclosed. In one example, an image sensing device includes a pixel unit cell with both event sensing (EVS) pixels and imaging pixels. The EVS and imaging pixels are configured to include event sensing and imaging pixel transistors formed in the same transistor layer of an integrated circuit assembly that also includes the photodiodes of the EVS and imaging pixels. The photodiodes are separated by a rear deep trench isolation (RDTI), and the EVS and imaging pixel transistors are arranged along (e.g., underneath) boundary areas formed by the RDTI, maximizing the space available for the photodiodes and economizing on wiring requirements for the EVS and imaging pixels.

Image sensing device with event based vision sensor pixels and imaging pixels

A pixelated image sensor capable of simultaneously supporting an EVS mode and an image-frame capture mode of operation. An individual pixel of the sensor comprises two distinct sets of subpixels involved in the two modes, respectively, and at least two corresponding, functionally different and independent electrical circuits. The metal interconnect structure of the image-sensor IC is implemented using a wiring topology in which spatial overlap between the wirings of the two electrical circuits is optimized (e.g., minimized) to reduce inter-circuit crosstalk when the two circuits are active at the same time. Such wiring topology may be beneficial, e.g., due to the resulting improvements in the image quality for both operating modes.

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Victor, NY, United States of America

Hongyi Mi