Yangtze Memory Technologies Co., Ltd.

Yangzte Memory Technologies., Ltd.

Hongtao Liu

Ying Huang

Wenzhe Wei

Lei Jin

Dejia Huang

Yali Song

XiangNan Zhao

Jianquan Jia

An Zhang

Song Min Jiang

Shan Li

Kaiwei Li

Xinlei Jia

Qiguang Wang

Kaikai You

Yuanyuan Min

Chenhui Li

Zhongwen Ling

Jichao Huang

Junqiang Xiong

Shuang Li

Lijun Teng

Yuan-Yuan Min

Wen Qing Chen

Ying Cui

Da Li

Zongliang Huo

Xiaojiang Guo

Hua Tan

Yi Zhang

Ke Liang

Feng Xu

Jialiang Deng

Zhipeng Dong

Ming Wang

Lei Guan

Ling Chu

Xuezhun Xie

Manxi Wang

Shiyu Xia

Songmin Jiang

Ting Cheng

Yongyan Xu

Zhiyu Wang

Wei Hou

Zhenjia Chen

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for operating a memory device having multiple storage modes. In one example method, a portion of a memory array is selected, wherein the portion of the memory array is programmable in a first storage mode or a second storage mode. The second storage mode has a lower storage density than the first storage mode, and the first storage mode corresponds to a first erase operation. A switch erase operation is performed to switch the portion of the memory array from the first storage mode to a switched second storage mode, wherein the switched second storage mode has the same storage density as the second storage mode and corresponds to the switch erase operation. The switch erase operation is different from the first erase operation on the memory array in the first storage mode.

Erase and program operations for memory devices having multiple storage modes

The present disclosure provides a configuration method and a reading method for a 3D memory, a 3D memory and system. The configuration method includes: writing test data into a plurality of selected memory cells corresponding to a selected word line in one of a plurality of memory blocks of the memory device; determining threshold voltages of the plurality of selected memory cells; and obtaining a relationship table indicating a corresponding relationship between a number of a subset of the selected memory cells that have threshold voltages lower than a preset voltage and a pass voltage required for performing a read operation on the one memory block.

Configuration method and reading method of 3D memory device, 3D memory device, and memory system

The present application discloses a memory, a memory system, and a method for operating memory, which belongs to the memory techniques field. The method for operating memory comprises determining a storage state of a reference memory cell, determining a discharge duration of a sensing node corresponding to a target memory cell based on the storage state of the reference memory cell, and reading the target memory cell based on the discharge duration of the sensing node corresponding to the target memory cell to obtain read results. The target memory cell and the reference memory cell are located in the same string and are adjacent, and the programming order of the reference memory cell is after that of the target memory cell. The present application may reduce the influence on reading memory cells by interlayer interference and improve the accuracy of reading memory cells.

Memory, a memory system, and a method for operating memory

A memory device includes a memory array including memory strings and a first word line, and a peripheral circuit coupled to the memory array. Each memory string includes a select gate transistor and memory cells. The peripheral circuit is configured to apply, during a first time period, a program voltage to the first word line to program a first memory cell in a selected memory string, apply, during a second time period after the first time period, a first verify voltage to the first word line to verify the first memory cell, compare the first verify voltage with a target voltage to obtain a comparing result, and in response to the comparing result indicative of the first verify voltage being higher than the target voltage, turn off, during a third time period between the first and the second time periods, the select gate transistor in an unselected memory string.

Memory device and program operation thereof

A programming method and a semiconductor device are provided. The semiconductor device includes a memory string that includes a plurality of first memory cells and a first dummy cell stacked in sequence, and each first memory cell is connected to a respective word line, and a gate of the first dummy cell is connected to a first dummy word line. The method includes: in a programming phase, applying a first pass voltage to a word line corresponding to a first unprogrammed memory cell, wherein the first unprogrammed memory cell is an unprogrammed memory cell of the plurality of first memory cells separated from a to-be-programmed memory cell by a first preset number of first memory cells; and after applying the first pass voltage to the word line corresponding to the first unprogrammed memory cell, applying a programming voltage to the word line corresponding to the to-be-programmed memory cell.

Programming method for semiconductor device and semiconductor device

A memory includes wordline (WL) layers and a controller coupled to the WL layers. The controller is configured to apply at least one verify voltage to a first WL layer of the WL layers during a verify phase, and apply a first pass voltage to a second WL layer of the WL layers during the verify phase. A first memory cell of the first WL layer is programmed before a second memory cell of the second WL layer. The first pass voltage is higher than a threshold voltage of a memory cell in a lowest programming state.

3D NAND flash and operation method thereof

A method of programming a memory device including a cell is provided. A first program pulse is applied to the cell. Middle program pulses are applied to the cell after the application of the first program pulse. A last program pulse is applied to the cell after the application of the middle program pulses. A pulse width of the last program pulse is wider than a pulse width of each of the middle program pulses and the first program pulse.

Control method and controller of 3D NAND flash

Upon determining that a first read operation on one memory cell of a plurality of memory cells has failed, a second read operation on the memory cell is started. In the second read operation, a second pass voltage is applied to first unselected word lines, and a first pass voltage is applied to second unselected word lines. The first unselected word lines include one or more word lines adjacent to a selected word line, and the second unselected word lines include remaining unselected word lines. The selected word line corresponds to the memory cell to be read. The first pass voltage includes a voltage applied to the first unselected word lines in the first read operation. The second pass voltage is higher than the first pass voltage.

Memory device, memory system, and read operation method thereof

Disclosure includes systems, methods and devices to program a memory device, involving a first and a second programming operations on a memory cell of the memory device. In the first programming operation, the memory cell is programmed into an intermediate state. In the second programming operation, the memory cell is programmed from the intermediate state into a target state. The first programming operation includes providing a bias voltage to a bit line coupled to the memory cell and providing a programming voltage to a word line coupled to the memory cell. An amplitude of the bias voltage provided to the bit line depends on the intermediate state or the target state the memory cell to be programmed into. Accordingly, no verification operation need to be performed on the memory cell in the first programming operation.

Memory device, memory system, and program method thereof

A three-dimensional (3D) memory device and method for reading the same are provided. The device includes memory cell strings each including multiple memory cells. In each memory cell string, a topmost memory cell is connected to a top selection gate connected to a bit line, and a bottommost memory cell is connected to a bottom selection gate. The method includes sequentially programming multiple memory cells in a memory cell string according to a programming sequence; in reading a memory cell, applying a corresponding bit line voltage to the memory cell string according to the programming sequence of the memory cell.

Three-dimensional memory device and method for reading the same

A memory device includes a memory array including memory strings, each memory string comprising a plurality of first memory cells, a plurality of second memory cells, and one or more dummy memory cells between the first memory cells and the second memory cells. The first memory cells are between drain terminals of the memory strings and the dummy memory cells, and the second memory cells are between source terminals of the memory strings and the dummy memory cells. The bit lines are respectively coupled to drain terminals of the memory strings. The word lines are respectively coupled to gate terminals of the first memory cells and the second memory cells. A word line driver is configured to apply a first voltage signal to each of the word lines that are coupled to the gate terminals of the first memory cells during a pre-charge phase.

Method of performing programming operation and related memory device

A programming method for a memory device is disclosed. The programming method comprises moving a plurality of first charge carriers at a shallow energy level to a channel in a substrate layer before a programming operation for a first word line, wherein the plurality of first charge carriers at the shallow energy level correspond to a memory cell to be programmed.

Memory device and programming method thereof

A memory device includes a memory string and a control circuit coupled to the memory string. The memory string includes a top select gate, word lines, and a bottom select gate. The control circuit is configured to, in an erasing operation, apply an erasing voltage to the memory string, apply a verifying voltage to at least one word line of the word lines after applying the erasing voltage to the memory string, and apply a first turn-on voltage to the bottom select gate, before applying the verifying voltage to the at least one word line.

Memory device and erasing and verification method thereof

A memory device includes a memory cell array and peripheral circuits. The memory cell array may include one or more first memory cells configured to store first type data, and one or more second memory cells configured to store second type data. The peripheral circuits may be coupled to the memory cell array and configured to perform a first program operation on the one or more first memory cells, perform the first program operation on the one or more second memory cells, and perform a second program operation on the one or more first memory cells. A first storage time corresponding to the first type data is longer than a second storage time corresponding to the second type data.

Memory device, memory system, and program operation method thereof

This disclosure provides a memory device, a memory system, and an operation method. The memory device includes a memory array having a plurality of memory blocks and a control circuit coupled to the memory array and used to control the memory array. The control circuit is configured to determine a first average value of threshold voltages of bottom dummy cells in an unused memory block, determine a difference value between the first average value and a first reference value, and judge based on the difference value when bottom dummy cells in the memory block are to be programmed so that the first average value reaches a first threshold.

Memory device, a memory system and an operation method

Growing community of inventors

Wuhan, China

Hongtao Liu