Tongfu Microelectronics Co., Ltd.

Nantong Fujitsu Microelectronics Co., Ltd.

Honghui Wang

Lei Shi

Yujuan Tao

Jing Wu

Chang-Ming Lin

Haizhong Shi

Xiaoyong Miao

A packaging structure and fabrication method thereof are provided. The method includes: providing semiconductor chips including soldering pads and metal bumps; providing a base plate, wiring structures, input terminals, and output terminals; mounting the semiconductor chips on the front surface of the base plate inversely, such that each metal bump is connected to a corresponding input terminal; forming a bottom filling layer between a functional surface of each semiconductor chip and the front surface of the base plate; forming a first shielding layer covering a non-functional surface and sidewalls of each semiconductor chip, and covering sidewalls of a corresponding bottom filling layer; forming a second shielding layer on each first shielding layer; forming a plastic encapsulation layer on second shielding layers and on a portion of the base plate between semiconductor chips; and forming external contact structures connected to the output terminals.

Packaging structure of semiconductor chip and formation method thereof

A system-level packaging method includes providing a packaging substrate having a first functional surface and a second surface with wiring arrangement within the packaging substrate and between the first functional surface and the second surface. The method also includes forming at least two package layers on the first functional surface of the packaging substrate, wherein each package layer is formed by subsequently forming a mounting layer, a sealant layer, and a wiring layer. Further, the method includes forming a top sealant layer and planting connection balls on the second functional surface of the packaging substrate.

System-level packaging structures

The present invention provides a structure and a method of reinforcing a conductor soldering point of a semiconductor device. The structure includes an inner frame lead, a soldering area arranged on the surface of the inner frame lead, a conductor soldered in the soldering area, and a locking card including a pressing part, a locking part overhangs outwards from the pressing part pressed on the conductor. The locking part penetrates through the inner frame lead and is clamped on the side of the inner frame lead deviating from the conductor. According to the present invention, the conductor soldered on the inner frame lead is firmly clamped on the inner frame lead through the locking card to effectively avoid the stripping condition of the conductor and the inner frame lead, reinforce the electrical connection of the conductor and the inner frame lead, and improve the reliability of the semiconductor device.

Structure and method of reinforcing a conductor soldering point of semiconductor device

System-level packaging methods and structures

A semiconductor device package and packaging method, the semiconductor device packaging method comprising: providing a chip with a bonding pad formed on the chip surface; forming a passivation layer and a bump on the chip surface, wherein the passivation layer has an opening exposing part of the pad, the bump is located in the opening and the size of the bump is less than the size of the opening; forming a solder ball covering the top surface and the side wall of the bump, and the bottom surface of the opening. The formed semiconductor device package is not easy to form a short circuit. The bonding strength between the solder ball and the bump is high and the performance of the semiconductor device is stable.

Metal contact for semiconductor device

A 3D system-level packaging method includes providing a packaging substrate, forming a glue layer on the substrate, and attaching a first chip layer at an opposite side of a functional surface of the first chip layer on the packaging substrate through the glue layer. The method also includes forming a first sealant layer on the packaging substrate at a same side attached with the first chip layer and exposing bonding pads of the first chip layer. The method also includes forming first vias in the first sealant layer, forming first vertical metal wiring in the first vias, and forming a first horizontal wiring layer on the sealant layer interconnecting the first chip layer and the first vertical metal wiring. Further, the method includes forming a plurality of package layers on the first sealant layer, and each of the plurality of package layers includes a chip layer, a sealant layer covering the chip layer, and vertical metal wiring and a horizontal wiring layer interconnecting adjacent package layers.

Growing community of inventors

Nantong, China

Honghui Wang