Applied Materials, Inc.

Lucent Technologies Inc.

Tensilica, Inc.

Xilinx, Inc.

Hongbin Ji

Inchen Huang

Quanyuan Shang

Janusz Jozwiak

John M White

Shinichi Kurita

Jun Yang

Ephrem C Wu

James Hoffman

Chung-Shin Kang

Emanual Beer

Michael Carchia

Fan Cheung Sze

Muralidharan Sampath Kodialam

Yung-Terng Wang

Rafael C Camarota

On-Ching Yue

Bassam Shamoun

Thomas H Strader

Rangarajan Srinivasan

Zbigniew Marek Dziong

Eraj D Kaluarachchi

Zhensheng Zhang

In embodiments of a digital lithography system, physical design data prepared at a data prep server in a hierarchical data structure. A leaf node comprises a repeater nod, comprising a bitmap image and a plurality of locations at which the bitmap appears in a physical design. At an EYE server, a repeater node bitmap is adjusted based upon, for example, spatial light modulator rotational adjustment and substrate distortion. The adjusted repeater node and the plurality of locations in which the adjusted repeater appears is compared to the repeater of the data prep server and its plurality of locations. In further embodiments, a rasterizer generates a checksum of bitmap to be printed to a substrate, from the EYE server bitmap. The checksum is compared to a checksum of the EYE server bitmap.

Data inspection for digital lithography for HVM using offline and inline approach

In disclosed circuit arrangements, memory cell arrays are addressed by a first portion of an input address, and memory cells within each memory cell array are addressed by a second portion of the input address. A first first-in-first-out (FIFO) buffer is coupled to the memory cell arrays and delays the second portion of each input address to the memory cell arrays for a sleep period. Control circuits respectively coupled to the memory cell arrays include second FIFO buffers and decode the first portion of each input address and generate corresponding states of enable signals. The control circuits store the corresponding states of the enable signals in the second FIFO buffers concurrently with input of the second portion of each input address to the first FIFO buffer. The second FIFO buffers delay output of the corresponding states of the enable signals to the memory cell arrays for the sleep period. Each control circuit further switches a corresponding memory cell array into a sleep mode in response to all states of the enable signal in the corresponding second FIFO buffer being in a non-enabled state.

Power control over memory cell arrays

An integrated circuit comprises a memory matrix including: a first memory cell array; a first multiplexer (MUX) coupled to an input of the first memory cell array; a second MUX coupled to an output of the first memory cell array; a second memory cell array; a third MUX coupled to an input of the second memory cell array; and a fourth MUX coupled to an output of the second memory cell array. The second MUX is coupled to the fourth MUX. The fourth MUX is configured to pass a selected one of: (1) an output from the third MUX, (2) an output from the second memory cell array, or (3) an output from the second MUX.

Memory matrix

In a first aspect, a first apparatus is provided for inkjet printing. The first apparatus includes an inkjet head support that includes a plurality of inkjet heads. A first inkjet head of the plurality of inkjet heads is adapted to be independently moveable in both directions along a lateral axis relative to a second inkjet head of the plurality of inkjet heads. The first apparatus also includes a system controller adapted to control an independent lateral movement of the first inkjet head relative to the second inkjet head. Numerous other aspects are provided.

Apparatus and methods for an inkjet head support having an inkjet head capable of independent lateral movement

In a first aspect, a system is provided. The system includes (1) a stage adapted to move a substrate relative to print heads during printing; (2) at least one print head suspended from a support above the stage and adapted to be moveable in a plane above the stage; (3) a controller operable to rotate the print head about a center of the print head; and (4) an imaging system adapted to capture an image of the print head and to determine a center point of the print head based upon images of the print head captured as the print head is rotated. Numerous other aspects are provided.

Methods and apparatus for aligning print heads

In some aspects, a method is provided for enhancing electronic device manufacturing throughput within an electronic device manufacturing tool. The method includes the steps of (1) for the electronic device manufacturing tool, creating an electronic device manufacturing schedule based on process factors and mechanical factors associated with the manufacturing tool; and (2) employing the electronic device manufacturing schedule during electronic device manufacturing within the electronic device manufacturing tool. Numerous other aspects are provided.

Methods and apparatus for enhancing electronic device manufacturing throughput

Methods, systems, and apparatus are provided that include determining a number of storage locations corresponding to busy chambers of an electronic device manufacturing tool; based on the number of storage locations corresponding to busy chambers, determining whether the electronic device manufacturing tool may accommodate a substrate; and of the electronic device manufacturing tool may accommodate a substrate, receiving a substrate in the electronic device manufacturing tool. Numerous other aspects are provided.

The present invention provides methods and apparatus for controlling the quantity of fluid output (e.g., drop size) by individual nozzles of a print head to a very high precision at a frequency equal to the frequency at which fluid is normally dispensed. This is achieved by mapping fluid quantity control information into the data that represents the image to be printed. Data representative of an image is received and converted into pixel data. In at least one embodiment, the pixel data includes pixels represented by N bits, and the N bits may represent a drop size for the pixel and a union of the N bits may represent a nozzle status. A print head may be controlled based on the pixel data, and the print head may include nozzles that are each adapted to deposit at least one drop size quantity of a fluid on a substrate.

Methods and apparatus for precision control of print head assemblies

Call admission methods for admitting connections into ATM/IP networks having a plurality of communication channels are disclosed. An overbooking technique is utilized which distinguishes among the different service classes. Each service class is assigned an overbooking factor. The call admission is determined based on the overbooking factor assigned to the class and the effective bandwidth for that service class. In addition, methods are disclosed for performing appropriate bookkeeping, i.e., updating and maintaining information concerning the state of the system.

Call admission control with overbooking support and cell loss ratio and cell delay variation guarantee

An advanced data structure allows lookup based upon the most significant 16 bits and the following variable number of K bits of the IP destination address. This 16/K scheme requires less than 2 MB memory to store the whole routing tables of present day backbone routers. A 16/Kc version utilizes bitmaps to compress the table to less than 0.5 MB. For the 16/K data structure each route lookup requires at most 2 memory accesses while the 16/Kc requires at most 3 memory accesses. By configuring the processor properly and developing a few customized instructions to accelerate route lookup, one can achieve 85 million lookups per second (MLPS) in the typical case with the processor running at 200 MHz. Further, the lookup method can be implemented using pipelining techniques to perform three lookups for three incoming packets simultaneously. Using such techniques, 100 MLPS performance can be achieved.

Fast IP route lookup with 16/K and 16/Kc compressed data structures

A novel solution for fast packet classification includes a novel data structure to store classifier rules which enables fast packet classification, which structure employs bitmaps for each field of the incoming packet for which classification is desired. A fast packet classification algorithm using the novel data structure allows the matching rule with the highest priority to be quickly obtained. A novel rule update algorithm allows new classifier rules to be added into the data structure incrementally. In one practical implementation of a classification engine employing the structures and algorithms of the present invention, a configurable processor with customized instructions is used to accelerate packet classification.

Fast IP packet classification with configurable processor

A novel compression method uses bitmaps to reduce the memory storage requirement of routing table information to about 3 MB. The data structure can be used for both route lookup and update. It does not require a separate data structure to be used for route update. A fast route lookup method is also disclosed. An efficient update method supports incremental route update. Through configuring a processor properly and developing a few customized instructions specifically for route lookup, the system can achieve more than 10 million lookups per second (MLPS) at 200 MHz. Using a configurable processor for route lookup/update provides more flexibility and extensibility which supports different data structures and lookup/update methods to meet application specific needs. The data structure and lookup method can be implemented in pure hardware in a pipelined fashion to achieve approximately 100 MLPS.

Fast IP route lookup with configurable processor and compressed routing table

Congestion across links in a network, such as the Internet, is reduced by diverting traffic from the congested link to alternative, shortest paths by adjusting splitting factors associated with the congested and alternative links. The alternative shortest paths comprise equal cost paths. Alternatively, adjustments occur after the creation of additional equal cost paths/shortest paths if none are initially available within the network. Unique programs control the adjustment of the splitting factors and the creation of the additional shortest paths. The programs make use of both existing, real networks and constructed, virtual networks in conjunction with novel traffic flow relationships to divert traffic from a congested link without causing further congestion within the network. Another unique program deletes shortest paths once used to accept traffic diverted from a congested link when traffic in the network decreases.

Methods and devices for relieving congestion in hop-by-hop routed packet networks

Tuning for connection admission control (CAC) algorithms in broadband ATM networks is accomplished using an overbooking technique based on aggregate effective bandwidth, AEBW, as an approximation to required bandwidth for given levels and classes of network traffic. An overbooking gain factor, &agr; is developed&mdash;typically in a network operations system&mdash;based on long-term measurements supplied periodically by network switches. In operation, overbooking is introduced in small increments until a threshold (such as a cell loss threshold) is reached, at which point overbooking is reduced in a large step. A variety of network measurements can be used to apply the present invention to a range of traffic and service contexts.

Growing community of inventors

San Jose, CA, United States of America

Hongbin Ji