Globalfoundries Inc.

Globalfoundries U.S. Inc.

Globalfoundries Singapore Pte. Ltd.

Other

Hong Yu

Zhenyu Hu

Haiting Wang

Hui Zang

Huang Liu

Jiehui Shu

Jianwei Peng

Judson Robert Holt

Alexander M Derrickson

Xinyuan Dou

Jinping Liu

Xusheng Kevin Wu

Wei Hong

Richard J Carter

Vibhor Jain

Hongliang Shen

Lun Zhao

Jin Ping Liu

Bingwu Liu

Zhao Lun

Wei Zhao

Hui Zhan

Xing Zhang

Hyucksoo Yang

Laertis Economikos

Shesh Mani Pandey

Haigou Huang

Yanping Shen

Man Gu

Anton Tokranov

Ruilong Xie

Jagar Singh

Alex See

Wei Lu

Scott Beasor

Jerome Ciavatti

Hsien-Ching Lo

Lup San Leong

Benfu Lin

Puneet Khanna

Rinus Tek Po Lee

Ashish Kumar Jha

Yanzhen Wang

Yongsik Moon

John Joseph Pekarik

Steven J Bentley

Viorel C Ontalus

Sipeng Gu

Yi Qi

Manfred Eller

Nicholas V Licausi

Guoxiang Ning

Xiang Hu

Randy W Mann

George Robert Mulfinger

Navneet Jain

David C Pritchard

Michael Vincent Aquilino

Guowei Xu

Dim-Lee Kwong

Liang-Choo Hsia

Jinsheng Gao

Edmund Kenneth Banghart

Domingo A Ferrer

Elizabeth Strehlow

Tao Han

Jae Gon Lee

Meisheng Zhou

Lakshmi Kanta Bera

Tao Chu

Meixiong Zhao

Sanjay Parihar

Yue Zhong

Jeffrey Chee

Byoung-Gi Min

Wang Zheng

Wen Zhi Gao

James Yongmeng Lee

James Mazza

Erik Geiss

Jay A Mody

Eric S Kozarsky

Seong Yeol Mun

Guoliang Zhu

Xiaoming Yang

Edward Reis

Yong Jun Shi

Feng Zhao

Dongil Choi

Charles Vanleuvan

Biao Zuo

Basab Banerjee

Ming-Fu Li

Edward P Reis, Jr

Wang Haiting

Harold Mendoza

Clynn J Mathew

Md Khaled Hassan

Yea-Sen Lin

A structure and method of forming different high dielectric constant (high-K) gate dielectrics for different transistors on the same substrate, are disclosed. A first region includes a first transistor(s) on the substrate having a first gate structure having a first gate body over a first high-K gate dielectric. The first gate body and the first high-K gate dielectric have different widths defining a first width difference. A second region includes a second transistor(s) on the substrate having a second gate structure having a second gate body over a second high-K gate dielectric. The second gate body and the second high-K gate dielectric have different widths defining a second width difference. The first width difference is different than the second width difference, i.e., amongst transistors in the different regions. The different gate dielectric widths improve control of overlap capacitance of the transistors without increasing dopants or an annealing temperature.

Structure having different gate dielectric widths in different regions of substrate

An apparatus has a first gate structure of a core device on a substrate, a first L-shaped spacer covering a sidewall of the first gate and part of the substrate adjacent to the first gate, a first raised source/drain (S/D) structure on the substrate and spaced apart from the first gate by the first L-shaped spacer, a second gate of an I/O device on the substrate, a second L-shaped spacer covering a sidewall of the second gate and part of the substrate adjacent to the second gate, and a second raised S/D structure spaced apart from the second gate by the second L-shaped spacer. The first and second L-shaped spacers have the same spacer width, and a distance between the first gate structure and a sidewall of the first S/D structure is less than a distance between the second gate structure and a sidewall of the second S/D structure.

Semiconductor device with different sized epitaxial structures

A structure is provided, the structure comprising a substrate and a first silicon germanium fin over the substrate. A first silicon germanium layer may be arranged in the substrate, whereby the first silicon germanium layer may be coupled to the first silicon germanium fin. A second silicon germanium layer may be arranged in the substrate, whereby the second silicon germanium layer may be coupled to the first silicon germanium fin.

Silicon germanium fins and integration methods

Structures for a transistor and methods of forming a structure for a transistor. The structure includes a first dielectric spacer, a second dielectric spacer, and a gate laterally between the first dielectric spacer and the second dielectric spacer. The gate includes a first silicide layer extending from the first dielectric spacer to the second dielectric spacer. The structure further includes a second silicide layer within the first silicide layer, and a contact that is aligned to the second silicide layer.

Transistors with multiple silicide layers

Device structures for a high-voltage semiconductor device and methods of forming such device structures. The structure comprises a layer stack including a first dielectric layer and a second dielectric layer. The first dielectric layer includes a portion between the second dielectric layer and a semiconductor substrate. The structure further comprises a field-effect transistor including a first source/drain region in the semiconductor substrate, a second source/drain region in the semiconductor substrate, and a gate electrode on the layer stack. The gate electrode is laterally between the first and second source/drain regions, and the gate electrode overlaps with the portion of the first dielectric layer and the second dielectric layer. The structure further comprises a spacer laterally between the first source/drain region and the second dielectric layer.

Device structures for a high-voltage semiconductor device

The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base having at least one sidewall with a gradient concentration of semiconductor material; an emitter on a first side of the extrinsic base; and a collector on a second side of the extrinsic base.

Lateral bipolar transistors

Structures for a bipolar junction transistor and methods of fabricating a structure for a bipolar junction transistor. The structure includes a collector having a first semiconductor layer, an emitter having a second semiconductor layer, an intrinsic base including nanosheet channel layers positioned with a spaced arrangement in a layer stack, and a base contact laterally positioned between the first and second semiconductor layers. Each nanosheet channel layer extends laterally from the first semiconductor layer to the second semiconductor layer. Sections of the base contact are respectively positioned in spaces between the nanosheet channel layers. The structure further includes first spacers laterally positioned between the sections of the base contact and the first semiconductor layer, and second spacers laterally positioned between the sections of the base contact and the second semiconductor layer.

Bipolar junction transistors with a nanosheet intrinsic base

A structure is provided, the structure may include an active layer arranged over a buried oxide layer, the active layer having a top surface. The top surface of the active layer may have a first portion and a second portion. A barrier stack may be arranged over the first portion of the top surface of the active layer. The barrier stack may include a barrier layer. The second portion of the top surface of the active layer may be adjacent to the barrier stack. A fin may be spaced from the first portion of the top surface of the active layer by the barrier stack, the fin having a first side surface, a second side surface opposite to the first side surface and a top surface. A dielectric layer may be arranged on the first side surface, the second side surface and the top surface of the fin, and the second portion of the top surface of the active layer. A metal layer may be arranged over the dielectric layer.

Fin on silicon-on-insulator

Device structures for a high-voltage semiconductor device and methods of forming such device structures. The structure comprises a semiconductor substrate and a layer stack including a first dielectric layer and a second dielectric layer. The first dielectric layer is positioned between the second dielectric layer and the semiconductor substrate. The structure further comprises a field-effect transistor including a first source/drain region in the semiconductor substrate, a second source/drain region in the semiconductor substrate, and a metal gate on the layer stack laterally between the first source/drain region and the second source/drain region. The second dielectric layer is positioned between the metal gate and the first dielectric layer. A contact extends through the layer stack to the first source/drain region.

High-voltage semiconductor device structures

Embodiments of the disclosure provide a bipolar transistor structure including a semiconductor fin on a substrate. The semiconductor fin has a first doping type, a length in a first direction, and a width in a second direction perpendicular to the first direction. A first emitter/collector (E/C) material is adjacent a first sidewall of the semiconductor fin along the width of the semiconductor fin. The first E/C material has a second doping type opposite the first doping type. A second E/C material is adjacent a second sidewall of the semiconductor fin along the width of the semiconductor fin. The second E/C material has the second doping type. A width of the first E/C material is different from a width of the second E/C material.

Bipolar transistor structure on semiconductor fin and methods to form same

The present disclosure generally relates to semiconductor structures and, more particularly, to single fin structures and methods of manufacture. The structure includes: an active single fin structure; a plurality of dummy fin structures on opposing sides of the active single fin structure; source and drain regions formed on the active single fin structure and the dummy fin structures; recessed shallow trench isolation (STI) regions between the dummy fin structures and the active single fin structure and below a surface of the dummy fin structures; and contacts formed on the source and drain regions of the active single fin structure with a spacing of at least two dummy fin structures on opposing sides of the contacts.

Single fin structures

Semiconductor structures include a channel region, a gate dielectric on the channel region, source and drain structures on opposite sides of the channel region, and a gate conductor between the source and drain structures on the gate dielectric. The source and drain structures include source and drain silicides. The gate conductor includes a gate conductor silicide. The gate conductor silicide is thicker than the source and drain silicides.

Carbon implantation for thicker gate silicide

Structures for a bipolar junction transistor and methods of fabricating a structure for a bipolar junction transistor. The structure includes a first terminal having a first raised semiconductor layer, a second terminal having a second raised semiconductor layer, and a base layer positioned laterally between the first raised semiconductor layer and the second raised semiconductor layer. The structure further includes a spacer positioned laterally positioned between the first raised semiconductor layer and the base layer. The spacer includes a dielectric material and an airgap surrounded by the dielectric material.

Lateral bipolar junction transistors with an airgap spacer

The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with thermal conductor and methods of manufacture. The structure includes: a base formed within a semiconductor substrate; a thermal conductive material under the base and extending to an underlying semiconductor material; an emitter on a first side of the base; and a collector on a second side of the base.

Bipolar transistor with thermal conductor

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Rexford, NY, United States of America

Hong Yu