Globalfoundries U.S. Inc.

Globalfoundries Inc.

Globalfoundries Singapore Pte. Ltd.

Other

Hong Yu

Zhenyu Hu

Haiting Wang

Hui Zang

Huang Liu

Jiehui Shu

Alexander M Derrickson

Jianwei Peng

Judson Robert Holt

Vibhor Jain

Xinyuan Dou

Jinping Liu

Xusheng Kevin Wu

Wei Hong

Richard J Carter

Hongliang Shen

Lun Zhao

Jin Ping Liu

David C Pritchard

Bingwu Liu

Man Gu

Zhao Lun

Wei Zhao

Hui Zhan

Xing Zhang

Hyucksoo Yang

Laertis Economikos

John Joseph Pekarik

Shesh Mani Pandey

Haigou Huang

Yanping Shen

Anton Tokranov

Ruilong Xie

Jagar Singh

Alex See

Venkatesh P Gopinath

Navneet Jain

Wei Lu

Scott Beasor

Jerome Ciavatti

Hsien-Ching Lo

Lup San Leong

Benfu Lin

Puneet Khanna

Rinus Tek Po Lee

Ashish Kumar Jha

Yanzhen Wang

Yongsik Moon

Steven J Bentley

Viorel C Ontalus

Sipeng Gu

Yi Qi

Manfred Eller

Nicholas V Licausi

Guoxiang Ning

Xiang Hu

Randy W Mann

George Robert Mulfinger

Michael Vincent Aquilino

Guowei Xu

Dim-Lee Kwong

Liang-Choo Hsia

Jinsheng Gao

Edmund Kenneth Banghart

Domingo A Ferrer

Elizabeth Strehlow

Tao Han

Jae Gon Lee

Meisheng Zhou

Tao Chu

Lakshmi Kanta Bera

Meixiong Zhao

Sanjay Parihar

Yue Zhong

James Mazza

Jeffrey Chee

Byoung-Gi Min

Wang Zheng

Wen Zhi Gao

James Yongmeng Lee

Erik Geiss

Jay A Mody

Guoliang Zhu

Eric S Kozarsky

Seong Yeol Mun

Shafiullah Syed

Xiaoming Yang

Romain Feuillette

Edward Reis

Yong Jun Shi

Feng Zhao

Dongil Choi

Charles Vanleuvan

Biao Zuo

Basab Banerjee

Ming-Fu Li

Edward P Reis, Jr

Heather Lazar

Harold Mendoza

Clynn J Mathew

A substrate is provided. The substrate includes a base, a semiconductor layer over the base, and an insulator layer between the base and the semiconductor layer. The semiconductor layer has a first semiconductor layer portion having a first thickness, a second semiconductor layer portion having a second thickness, and a third semiconductor layer portion having a third thickness, and the first thickness, the second thickness, and the third thickness are different from each other.

Substrates of semiconductor devices having varying thicknesses of semiconductor layers

Structures for a memory device and methods of forming a structure for a memory device. The structure comprises a first transistor including a first gate structure and a first source/drain region, a second transistor including a second gate structure and a second source/drain region, and a capacitor including a first capacitor plate directly coupled to the first source/drain region, a second capacitor plate, and a capacitor dielectric layer between the first capacitor plate and the second capacitor plate.

Memory device structures that include a capacitor

The present disclosure relates to semiconductor structures and, more particularly, to a multi-channel replacement metal gate device and methods of manufacture. The structure includes: a fully depleted semiconductor on insulator substrate; a plurality of fin structures over the fully depleted semiconductor on insulator substrate; and a metal gate structure spanning over the plurality of fin structures and the fully depleted semiconductor on insulator substrate.

Multi-channel replacement metal gate device

Structures that include bipolar junction transistors and methods of forming such structures. The structure comprises a substrate having a top surface, a trench isolation region in the substrate, and a base layer on the top surface of the substrate. The base layer extending across the trench isolation region. A first bipolar junction transistor includes a first collector in the substrate and a first emitter on a first portion of the first base layer. The first portion of the first base layer is positioned between the first collector and the first emitter. A second bipolar junction transistor includes a second collector in the substrate and a second emitter on a second portion of the first base layer. The second portion of the first base layer is positioned between the second collector and the second emitter.

Array arrangements of vertical bipolar junction transistors

Structures that include bipolar junction transistors and methods of forming such structures. The structure comprises a semiconductor layer, a substrate, and a dielectric layer disposed between the semiconductor layer and the substrate. The structure further comprises a first bipolar junction transistor including a first collector in the substrate, a first emitter, and a first base layer. The first base layer extends through the dielectric layer from the first emitter to the first collector. The structure further comprises a second bipolar junction transistor including a second collector in the substrate, a second emitter, and a second base layer. The second base layer extends through the dielectric layer from the second emitter to the second collector. The second base layer is connected to the first base layer by a section of the semiconductor layer to define a base line.

Bipolar junction transistor arrays

A semiconductor device is provided. The semiconductor device includes a substrate, a first gate electrode, a second gate electrode, and an isolation structure. The first gate electrode is over the substrate and the second gate electrode is laterally adjacent thereto. The isolation structure is in contact with the first gate electrode and the second gate electrode.

Isolation structures of semiconductor devices

A structure and method of forming different high dielectric constant (high-K) gate dielectrics for different transistors on the same substrate, are disclosed. A first region includes a first transistor(s) on the substrate having a first gate structure having a first gate body over a first high-K gate dielectric. The first gate body and the first high-K gate dielectric have different widths defining a first width difference. A second region includes a second transistor(s) on the substrate having a second gate structure having a second gate body over a second high-K gate dielectric. The second gate body and the second high-K gate dielectric have different widths defining a second width difference. The first width difference is different than the second width difference, i.e., amongst transistors in the different regions. The different gate dielectric widths improve control of overlap capacitance of the transistors without increasing dopants or an annealing temperature.

Structure having different gate dielectric widths in different regions of substrate

An apparatus has a first gate structure of a core device on a substrate, a first L-shaped spacer covering a sidewall of the first gate and part of the substrate adjacent to the first gate, a first raised source/drain (S/D) structure on the substrate and spaced apart from the first gate by the first L-shaped spacer, a second gate of an I/O device on the substrate, a second L-shaped spacer covering a sidewall of the second gate and part of the substrate adjacent to the second gate, and a second raised S/D structure spaced apart from the second gate by the second L-shaped spacer. The first and second L-shaped spacers have the same spacer width, and a distance between the first gate structure and a sidewall of the first S/D structure is less than a distance between the second gate structure and a sidewall of the second S/D structure.

Semiconductor device with different sized epitaxial structures

A structure is provided, the structure comprising a substrate and a first silicon germanium fin over the substrate. A first silicon germanium layer may be arranged in the substrate, whereby the first silicon germanium layer may be coupled to the first silicon germanium fin. A second silicon germanium layer may be arranged in the substrate, whereby the second silicon germanium layer may be coupled to the first silicon germanium fin.

Silicon germanium fins and integration methods

Structures for a transistor and methods of forming a structure for a transistor. The structure includes a first dielectric spacer, a second dielectric spacer, and a gate laterally between the first dielectric spacer and the second dielectric spacer. The gate includes a first silicide layer extending from the first dielectric spacer to the second dielectric spacer. The structure further includes a second silicide layer within the first silicide layer, and a contact that is aligned to the second silicide layer.

Transistors with multiple silicide layers

Device structures for a high-voltage semiconductor device and methods of forming such device structures. The structure comprises a layer stack including a first dielectric layer and a second dielectric layer. The first dielectric layer includes a portion between the second dielectric layer and a semiconductor substrate. The structure further comprises a field-effect transistor including a first source/drain region in the semiconductor substrate, a second source/drain region in the semiconductor substrate, and a gate electrode on the layer stack. The gate electrode is laterally between the first and second source/drain regions, and the gate electrode overlaps with the portion of the first dielectric layer and the second dielectric layer. The structure further comprises a spacer laterally between the first source/drain region and the second dielectric layer.

Device structures for a high-voltage semiconductor device

The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base having at least one sidewall with a gradient concentration of semiconductor material; an emitter on a first side of the extrinsic base; and a collector on a second side of the extrinsic base.

Lateral bipolar transistors

Structures for a bipolar junction transistor and methods of fabricating a structure for a bipolar junction transistor. The structure includes a collector having a first semiconductor layer, an emitter having a second semiconductor layer, an intrinsic base including nanosheet channel layers positioned with a spaced arrangement in a layer stack, and a base contact laterally positioned between the first and second semiconductor layers. Each nanosheet channel layer extends laterally from the first semiconductor layer to the second semiconductor layer. Sections of the base contact are respectively positioned in spaces between the nanosheet channel layers. The structure further includes first spacers laterally positioned between the sections of the base contact and the first semiconductor layer, and second spacers laterally positioned between the sections of the base contact and the second semiconductor layer.

Bipolar junction transistors with a nanosheet intrinsic base

A structure is provided, the structure may include an active layer arranged over a buried oxide layer, the active layer having a top surface. The top surface of the active layer may have a first portion and a second portion. A barrier stack may be arranged over the first portion of the top surface of the active layer. The barrier stack may include a barrier layer. The second portion of the top surface of the active layer may be adjacent to the barrier stack. A fin may be spaced from the first portion of the top surface of the active layer by the barrier stack, the fin having a first side surface, a second side surface opposite to the first side surface and a top surface. A dielectric layer may be arranged on the first side surface, the second side surface and the top surface of the fin, and the second portion of the top surface of the active layer. A metal layer may be arranged over the dielectric layer.

Fin on silicon-on-insulator

Device structures for a high-voltage semiconductor device and methods of forming such device structures. The structure comprises a semiconductor substrate and a layer stack including a first dielectric layer and a second dielectric layer. The first dielectric layer is positioned between the second dielectric layer and the semiconductor substrate. The structure further comprises a field-effect transistor including a first source/drain region in the semiconductor substrate, a second source/drain region in the semiconductor substrate, and a metal gate on the layer stack laterally between the first source/drain region and the second source/drain region. The second dielectric layer is positioned between the metal gate and the first dielectric layer. A contact extends through the layer stack to the first source/drain region.

High-voltage semiconductor device structures

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Rexford, NY, United States of America

Hong Yu