Sharp Laboratories of America, Inc

Lsi Corporation

Lsi Logic Corporation

Sharp Kabushiki Kaisha Corporation

Hong Ying

Sheng Teng Hsu

Fengyan Zhang

Tingkai Li

Sey-Shing Sun

Hemanshu D Bhatt

Jayanthi Pallinti

Dilip Vijay

Chiyi Kao

Bruce Dale Ulrich

Yoshi Ono

Peter Austin Burke

Yanjun Ma

Jer-shen Maa

Douglas James Tweet

Qwai Hoong Low

Chuan-Cheng Cheng

Peter J Wright

Ramaswamy Ranganathan

Sethuraman Lakshminarayanan

Passivation integration schemes and pad structures to reduce the stress gradients and/or improve the contact surface existing between the Al in the pad and the gold wire bond. One of the pad structures provides a plurality of recessed pad areas which are formed in a single aluminum pad. An oxide mesa can be provided under the aluminum pad. Another pad structure provides a single recessed pad area which is formed in a single aluminum pad, and the aluminum pad is disposed above a copper pad and a plurality of trench/via pads. Still another pad structure provides a single recessed pad area which is formed in a single aluminum pad, and the aluminum pad is disposed above a portion of a copper pad, such that the aluminum pad and the copper pad are staggered relative to each other.

Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing

A pad structure and passivation scheme which reduces or eliminates IMC cracking in post wire bonded dies during Cu/Low-k BEOL processing. A thick 120 nm barrier layer can be provided between a 1.2 &#x3bc;m aluminum layer and copper. Another possibility is to effectively split up the barrier layer, where the aluminum layer is disposed between the two barrier layers. The barrier layers may be 60 nm while the aluminum layer which is disposed between the barrier layers may be 0.6 &#x3bc;m. Another possibility is provide an extra 0.6 &#x3bc;m aluminum layer on the top barrier layer. Still another possibility is to provide an extra barrier layer on the top-most aluminum layer, such that a top barrier layer of 60 nm is provided on a 0.6 &#x3bc;m aluminum layer, followed by another harrier layer of 60 nm, another aluminum layer of 0.6 &#x3bc;m and another barrier layer of 60 nm.

Reduction of macro level stresses in copper/low-K wafers

Different ways to reduce or eliminate the IMC cracking issues in wire bonded parts, including: changing to more compressive dielectric films for top, R1, and R2; changing the top passivation film stacks to more compressive films; changing the low k film to a higher compressive film; reducing the R layer thickness and pattern density to reduce tensile stress; and minimizing anneal and dielectric deposition temperatures. Each of the methods can be used individually or in combination with each other to reduce overall tensile stresses in the Cu/low-k wafer thus reducing or eliminating the IMC cracking issue currently seen in the post wire bonded parts.

Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processing

A bond pad structure which includes an aluminum bond pad which include one or more dopants that effectively control the growth of IMC to a nominal level in spite of high tensile stresses in the wafer. For example, aluminum can be doped with 1&#x2013;2 atomic % of Mg. Alternatively, Pd or Si can be used, or elements like Cu or Si can be used as the dopant in order to reduce the overall tensile stresses in the wafer. This can control the abnormal growth of IMC, thus arresting the IMC crack formation. A combination of dopants can be used to both control the tensile stresses and also slightly alter the gold-Aluminum interface thus enabling a uniform and thin IMC formation. This tends to reduce or eliminate any voiding or cracking which would otherwise occur at the wire bond transfer.

Reduce or eliminate IMC cracking in post wire bonded dies by doping aluminum used in bond pads during Cu/Low-k BEOL processing

An electrode for use in a ferroelectric device includes a bottom electrode; a ferroelectric layer; and a top electrode formed on the ferroelectric layer and formed of a combination of metals, including a first metal take from the group of metals consisting of platinum and iridium, and a second metal taken from the group of metals consisting of aluminum and titanium; wherein the top electrode acts as a passivation layer and wherein the top electrode remains conductive following high temperature annealing in a hydrogen atmosphere. A method of forming a hydrogen-resistant electrode in a ferroelectric device includes forming a bottom electrode; forming a ferroelectric layer on the bottom electrode; depositing a top electrode on the ferroelectric layer; including depositing, simultaneously, a first metal taken from the group of metals consisting of platinum and iridium; and a second metal taken from the group of metals consisting of aluminum and titanium; and forming a passivation layer by annealing the structure in an oxygen atmosphere to form an oxide passivation layer on the top electrode.

Electrode materials with improved hydrogen degradation resistance

Low resistance interconnect lines and methods for fabricating them are described herein. IC fabrication processes are used to create interconnect lines of Al and Cu layers. The Cu layer is thinner than in the known art, but in combination with the Al layer, the aggregate Cu/Al resistance is lowered to a point where it is comparable to that of a very thick Cu layer, without the additional cost and yield problems caused by using a thicker Cu deposition. Fuses for memory repair can also be fabricated using the methods taught by the present invention with only small variations in the process.

Low resistance metal interconnect lines and a process for fabricating them

A passivation layer comprises a titanium-doped aluminum oxide layer for passivation of ferroelectric materials such as Pt/SBt/Ir&mdash;Ta&mdash;O devices. The titanium-doped aluminum oxide layer for passivation of ferroelectric materials has reduced stress and improved passivation properties, and is easy to deposit and be oxidized. The passivation layer in the MFM Structure resists breakdown and peeling during annealing of the device in a forming gas ambient.

Method and device using titanium doped aluminum oxide for passivation of ferroelectric materials

A MFMOS one transistor memory structure for ferroelectric non-volatile memory devices includes a high dielectric constant material such as ZrO , HfO , Y O , or La O , or the like, or mixtures thereof, to reduce the operation voltage and to increase the memory window and reliability of the device.

MFMOS capacitors with high dielectric constant materials

Method of using titanium doped aluminum oxide for passivation of ferroelectric materials and devices including the same

A semiconductor structure includes, on a SOI substrate, a CMOS formed on the substrate; and a SiGe HBT formed on the substrate. A method of fabricating a semiconductor structure includes preparing a SOI substrate having plural active regions thereon; forming a CMOS on the SOI substrate in a first active region; and forming a SiGe HBT on the SOI substrate in another active region.

Method of fabricating high performance SiGe heterojunction bipolar transistor BiCMOS on a silicon-on-insulator substrate

A method of forming an electrode in an integrated circuit includes preparing a silicon-base substrate, including forming semiconductor structures on the substrate to form an integrated substrate structure; depositing a layer of electrode material on a substrate structure; patterning the layer of electrode material to form electrode elements, wherein said patterning includes plasma etching the layer of electrode material in a plasma reactor in an etching gas atmosphere having a fluorine component therein; and cleaning the substrate structure and electrode elements in a distilled water bath.

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San Jose, CA, United States of America

Hong Ying