Taiwan Semiconductor Manufacturing Comp. Ltd.

Hong-Ye Shih

Wen-Chih Chiou

Tsang-Jiuh Wu

Ming-Tsu Chung

Ku-Feng Yang

Hsin-Yu Chen

Yung-Chi Lin

Chia-Yin Chen

Jiung Wu

HsiaoYun Lo

Chen-Hua Douglas Yu

Shin-Puu Jeng

Kuan-Liang Lai

Yi-Hsiu Chen

Ebin Liao

Chen-Yu Tsai

Jia-Ling Ko

A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.

Semiconductor device having backside interconnect structure on through substrate via

The disclosure provides a method of forming a package structure, and the method includes: bonding a die to a wafer; performing a thinning process on the die, wherein the die has a first total thickness variation (TTV) after performing the thinning process; forming a dielectric layer on the wafer to cover sidewalls and a top surface the die; performing a first removal process to remove a first portion of the dielectric layer and expose the top surface of the die; and performing a second removal process to remove a second portion of the dielectric layer and a portion of the die, wherein after performing the second removal process, the die has a second TTV less than the first TTV.

Package structure and method of forming the same

Method of forming semiconductor device having backside interconnect structure on through substrate via

Semiconductor device having backside interconnect structure on through substrate via and method of forming the same

An interconnect structure for an integrated circuit, such as a three dimensional integrated circuit (3DIC), and a method of forming the same is provided. An example interconnect structure includes a substrate, a through via extending through the substrate, and a liner disposed between the substrate and the through via. The substrate includes a tapered profile portion. The tapered profile portion abuts the liner.

Profile of through via protrusion in 3DIC interconnect

Provided is a 3DIC structure includes a wafer, a die and a dielectric layer. The die is over and bonded to the wafer. The dielectric layer is over the wafer and aside the die, covering sidewalls of the die. A total thickness variation (TTV) of the die is less than 0.8 &#x3bc;m.

Three-dimensional integrated circuit structure and method of manufacturing the same

An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value.

Self-alignment for redistribution layer

Semiconductor device having backside interconnect structure through substrate via and method of forming the same

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Taipei, Taiwan

Hong-Ye Shih