Sandisk Technologies Inc.

Micron Technology Incorporated

Hong-Yan Chen

Yingda Dong

Wei Zhao

Ching-Huang Lu

Tomoko Ogura Iwasaki

Henry Chin

Liang Pang

Erwin E Yu

Charles S Kwong

Kalyan Chakravarthy Kavalipurapu

Yunfei Xu

Jiahui Yuan

Ashish Kumar Baraskar

Zhengyi Zhang

Nan Lu

Yen-Lung Li

Priya Vemparala Guruswamy

Xiangyu Yang

Pamela Castalino

Control logic in a memory device causes a program voltage to be applied to a selected data wordline of a plurality of wordlines of a block of a memory array for a pulse duration period during a programming operation. The control logic further causes a first pass voltage to be applied to one or more unselected data wordlines of the plurality of wordlines of the block for the pulse duration period and causes a second pass voltage to be applied to a last unselected data wordline of the plurality of wordlines of the block for at least a first portion of the pulse duration period, wherein the second pass voltage has a lower magnitude than the first pass voltage.

Program scheme for edge data wordlines in a memory device

A program operation is initiated to program a set of target memory cells of a target wordline of a memory device to a target programming level. During a program verify operation of the program operation, a program verify voltage level is caused to be applied to the target wordline to verify programming of the set of target memory cells. A pass through read voltage level associated with the target wordline is identified. During the program verify operation, a pass through voltage level is caused to be applied to at least one of a first wordline or a second wordline, wherein the pass through read voltage level is the read voltage level reduced by an offset value.

Corrective program verify operation with improved read window budget retention

Control logic in a memory device cause a programming pulse to be applied to a set of wordlines including a first set of even-numbered wordlines corresponding to a first set of memory cells to be erased and a second set of odd-numbered wordlines corresponding to a second set of memory cells to be erased, where a set of electrons are injected into a first set of gate regions, a second set of gate regions, and a set of inter-cell regions of a charge trap (CT) layer of the memory device. The control logic executes a first erase cycle on the first set of even-numbered wordlines to remove a first subset of electrons from the first set of gate regions corresponding to the first set of even-numbered wordlines. The control logic executes a second erase cycle on the second set of odd-numbered wordlines to remove a second subset of electrons from the second set of gate regions corresponding to the second set of even-numbered wordlines.

Erase operation with electron injection for reduction of cell-to-cell interference in a memory sub-system

A processing device in a memory system connects a first data block of the memory device to a second data block of the memory device to generate a combined data block comprising a first plurality of sub-blocks of the first data block and a second plurality of sub-blocks of the second data block, wherein the connecting includes: for each wordline of a first plurality of wordlines of the first data block, creating a wordline connection short between the respective wordline of the first data block and a corresponding wordline of a second plurality of wordlines of the second data block, wherein the first plurality of wordlines and the second plurality of wordlines comprise data wordlines; and driving a first data wordline of the first data block and a second wordline of the second data block using a single string driver of the memory device.

Managing sub-block erase operations in a memory sub-system

A memory device includes unselected sub-block, which includes bit line; drain select (SGD) transistor coupled with bit line; a source voltage line; source select (SGS) transistor coupled with source voltage; and wordlines coupled with gates of string of cells, which have channel coupled between the SGS/SGD transistors. Control logic coupled with unselected sub-block is to: cause the SGD/SGS transistors to turn on while ramping the wordlines from a ground voltage to a pass voltage associated with unselected wordlines in preparation for read operation; cause, while ramping the wordlines, the channel to be pre-charged by ramping voltages on the bit line and the source voltage line to a target voltage that is greater than a source read voltage level; and in response to wordlines reaching the pass voltage, causing the SGD and SGS transistors to be turned off, to leave the channel pre-charged to the target voltage during the read operation.

Unselected sub-block source line and bit line pre-charging to reduce read disturb

A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline.

Control logic in a memory device initiates a program operation on the memory device, and causes a program voltage to be applied to a selected wordline of the memory array during a program phase of the program operation. The control logic further causes a select gate drain coupled with a string of memory cells in the memory array to deactivate during a recovery phase after applying the program voltage, wherein the string of memory cells comprises a plurality of memory cells, and wherein each memory cell of the plurality of memory cells is coupled to a corresponding wordline of a plurality of wordlines in the memory array.

Short program verify recovery with reduced programming disturbance in a memory sub-system

Control logic in a memory device initiates a program operation on the memory device, the program operation comprising a program phase, a program recovery phase, a program verify phase, and a program verify recovery phase. The control logic further causes a negative voltage signal to be applied to a first plurality of word lines of a data bock of the memory device during the program verify recovery phase of the program operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation and one or more data word lines adjacent to the selected word line.

Control logic in a memory device initiates, subsequent to a program verify phase of a program operation, a new program operation on the memory array, the new program operation comprising a pre-boosting phase occurring prior to a program phase. The control logic causing one or more positive pre-boosting voltages to be applied to corresponding subsets of a plurality of word lines of a block of the memory array during the pre-boosting phase and causes the one or more positive pre-boosting voltages to be ramped down to a ground voltage during the pre-boosting phase in a designated order based on a location of the corresponding subsets of the plurality of word lines to which the one or more positive pre-boosting voltages were applied.

Pre-boosting scheme during a program operation in a memory sub-system

A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline by an amount equal to a step down interval.

Control logic in a memory device initiates a program operation on the memory device, the program operation comprising a program phase, a program recovery phase, a program verify phase, and a program verify recovery phase. The control logic further causes a negative voltage signal to be applied to a first plurality of word lines of a data block of the memory device during the program verify recovery phase of the program operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation and one or more data word lines adjacent to the selected word line.

Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a pre-boosting phase occurring prior to a program phase. The control logic causes a first positive pre-boosting voltage to be applied to a first plurality of word lines of a data block of the memory array during the pre-boosting phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation. The control logic causes a second positive pre-boosting voltage to be applied to a second plurality of word lines of the data block during the pre-boosting phase, wherein the second plurality of word lines is adjacent to the first plurality of wordlines, wherein each of the second plurality of word lines is coupled to a corresponding memory cell of a second plurality of memory cells in the string of memory cells, and wherein the second positive pre-booting voltage has a lower magnitude than the first positive pre-boosting voltage. The control logic further causes the second positive pre-boosting voltage to be ramped down to a ground voltage during the pre-boosting phase prior to the first positive pre-boosting voltage being ramped down to the ground voltage.

Techniques are described for reducing an injection type of program disturb in a memory device during the pre-charge phase of a program loop. In one approach, a pre-charge voltage on the selected word line and drain side word lines is adjusted based on a risk of the injection type of program disturb. Risk factors such as temperature, WLn position, Vpgm and the selected sub-block, can be used to set the pre-charge voltage to be lower when the risk is higher. In another approach, the pre-charge voltage on the source side word lines is adjusted to reduce a channel gradient and/or the amount of time in which the injection type of program disturb occurs.

Method of reducing injection type of program disturb during program pre-charge in memory device

Techniques are described for maintaining a pre-charge voltage in a NAND string in a program operation. After a pre-charge voltage is applied to the channel of a NAND string, the word line voltages are controlled to avoid a large channel gradient which generates electron-hole pairs, where the electrons can pull down the channel boosting level on the drain side of the selected word line. In one approach, the word line voltages of a group of one or more source side word lines adjacent to the selected word line are increased directly from the level used during pre-charge to a pass voltage. The word line voltages of other source side word lines, and of drain side word lines, can be decreased and then increased to the pass voltage to provide a large voltage swing which couples up the channel.

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San Jose, CA, United States of America

Hong-Yan Chen