Adeia Semiconductor Bonding Technologies Inc.

Skyworks Solutions, Inc.

Other

Adeia Semiconductor Technologies LLC

Invensas LLC

Woburn, Inc.

Hong Shen

Liang Wang

Rajesh Katkar

Arkalgud R Sitaram

Cyprian Emeka Uzoh

Guilian Gao

Charles Gerard Woychik

Zhuowen Sun

Jiro Yota

Viswanathan Ramanathan

Belgacem Haba

Laura Wills Mirkarimi

Peter J Zampardi

Gabriel Z Guevara

Akash Agrawal

Hsiang-Chih Sun

Jens Albrecht Riege

Mehran Janani

David Steven Ripley

Philip John Lehtola

Patrick J Variot

Hongxiao Shao

Scott P McGrath

Matthew Ozalas

Tin Myint Ko

Weimin Sun

Anthony James Lobianco

Hoang Mong Nguyen

Ashok S Prabhu

Howard E Chen

Dinhphuoc Vu Hoang

Guohao Zhang

Matthew Sean Read

Reynaldo Co

Hardik Bhupendra Modi

Robert W Warren

Bongsub Lee

Sandra Louise Petty-Weeks

Sangil Lee

Patrick Lawrence Welch

Yifan Guo

Sitaram R Arkalgud

Patrick Variot

Ravi Ramanathan

Qiuliang Luo

Usama K Abdali

Matthew Thomas Ozalas

A microelectronic device may include a substrate, a first chip on the substrate, and a second chip on the substrate. A plurality of pillars may be located between the first chip and the second chip, wherein a first end of each pillar of the plurality of pillars is adjacent to the substrate. A spacing among the plurality of pillars is at least equal to a distance sufficient to block electromagnetic interference (EMI) and/or radio frequency interference (RFI) between the first chip and the second chip. The microelectronic device may also include a cover over at least the first chip, the second chip, and the plurality of pillars, wherein a second end of each pillar of the plurality of pillars is at least adjacent to a trench defined within the cover. The trench may include a conductive material therein.

Method of forming a region shielding within a package of a microelectronic device

One aspect of this disclosure is a power amplifier module that includes a power amplifier, a semiconductor resistor, a tantalum nitride terminated through wafer via, and a conductive layer electrically connected to the power amplifier. The semiconductor resistor can include a resistive layer that includes a same material as a layer of a bipolar transistor of the power amplifier. A portion of the conductive layer can be in the tantalum nitride terminated through wafer via. The conductive layer and the power amplifier can be on opposing sides of a semiconductor substrate. Other embodiments of the module are provided along with related methods and components thereof.

Power amplifier modules including semiconductor resistor and tantalum nitride terminated through wafer via

A method of manufacturing a microelectronic package with an integrally formed electromagnetic interference ('EMI') shield and/or antenna is disclosed. The method comprises patterning a conductive structure to comprise a base, a plurality of interconnection elements, and a die attach area sized to receive a microelectronic element; bonding ends of the plurality of interconnection elements to a carrier; encapsulating the plurality of interconnection elements, and the microelectronic element with an encapsulant; removing the carrier to expose free ends of the plurality of interconnection elements; patterning the exposed outer surface of the conductive structure overlying the microelectronic element to form a portion of the EMI shield structure and/or an antenna. The portion of the EMI shield structure and/or antenna can be patterned to extend continuously from one or more of the plurality of interconnection elements.

3D-interconnect with electromagnetic interference ('EMI') shield and/or antenna

Region shielding within a package of a microelectronic device

A method of fabricating an electronics package includes forming a cavity in a first surface of a semiconductor substrate, forming one or more passive devices on the semiconductor substrate, forming a microelectromechanical device on a piezoelectric substrate, and bonding the semiconductor substrate to the piezoelectric substrate with the microelectromechanical device disposed within the cavity.

Wafer level chip scale filter packaging using semiconductor wafers with through wafer vias

An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.

Integrated interposer solutions for 2D and 3D IC packaging

Dies () with integrated circuits are attached to a wiring substrate (), possibly an interposer, and are protected by a protective substrate () attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided.

Integrated circuits protected by substrates with cavities, and methods of manufacture

Systems and methods for providing 3D wafer assembly with known-good-dies are provided. An example method compiles an index of dies on a semiconductor wafer and removes the defective dies to provide a wafer with dies that are all operational. Defective dies on multiple wafers may be removed in parallel, and resulting wafers with all good dies stacked in 3D wafer assembly. In an implementation, the spaces left by removed defective dies may be filled at least in part with operational dies or with a fill material. Defective dies may be replaced either before or after wafer-to-wafer assembly to eliminate production of defective stacked devices, or the spaces may be left empty. A bottom device wafer may also have its defective dies removed or replaced, resulting in wafer-to-wafer assembly that provides 3D stacks with no defective dies.

System and method for providing 3D wafer assembly with known-good-dies

According to various aspects and embodiments, a method for forming a packaged electronic device is provided. In accordance with one embodiment, the method comprises depositing a layer of temporary adhesive material on at least a portion of a surface of a first substrate having a coefficient of thermal expansion, depositing a layer of dielectric material on at least a portion of the layer of temporary adhesive material, forming at least one seal ring on at least a portion of the layer of dielectric material, providing a second substrate having a coefficient of thermal expansion that is substantially the same as the coefficient of thermal expansion of the first substrate, the second substrate having at least one bonding structure attached to a surface of the second substrate, and aligning the at least one seal ring to the at least one bonding structure and bonding the first substrate to the second substrate.

Device packaging using a recyclable carrier substrate

A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.

Structures and methods for reliable packages

A contact pad includes a solder-wettable porous network () which wicks the molten solder () and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

Contact structures with porous networks for solder connections, and methods of fabricating same

HD color video using monochromatic CMOS image sensors integrated in a 3D package is provided. An example 3DIC package for color video includes a beam splitter to partition received light of an image stream into multiple light outputs. Multiple monochromatic CMOS image sensors are each coupled to one of the multiple light outputs to sense a monochromatic image stream at a respective component wavelength of the received light. Each monochromatic CMOS image sensor is specially constructed, doped, controlled, and tuned to its respective wavelength of light. A parallel processing integrator or interposer chip heterogeneously combines the respective monochromatic image streams into a full-spectrum color video stream, including parallel processing of an infrared or ultraviolet stream. The parallel processing of the monochromatic image streams provides reconstruction to HD or 4K HD color video at low light levels. Parallel processing to one interposer chip also enhances speed, spatial resolution, sensitivity, low light performance, and color reconstruction.

HD color imaging using monochromatic CMOS image sensors integrated in 3D package

An interposer () has contact pads at the top and/or bottom surfaces for connection to circuit modules (e.g. ICs). The interposer includes a substrate made of multiple layers (). Each layer can be a substrate (S), possibly a ceramic substrate, with circuitry. The substrates extend vertically. Multiple interposers are fabricated in a single structure () made of vertical layers () corresponding to the interposers' layers. The structure is diced along horizontal planes () to provide the interposers. An interposer's vertical conductive lines (similar to through-substrate vias) can be formed on the substrates' surfaces before dicing and before all the substrates are attached to each other. Thus, there is no need to make through-substrate holes for the vertical conductive lines. Non-vertical features can also be formed on the substrates' surfaces before the substrates are attached to each other. Other embodiments are also provided.

Interconnection substrates for interconnection between circuit modules, and methods of manufacture

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Palo Alto, CA, United States of America

Hong Shen