International Business Machines Corporation

Shanghai Ic R&d Center Co., Ltd

Chengdu Image Design Technology Co., Ltd.

Hong Lin

Huilong Zhu

Qin Yue Chen

Ehud Aharoni

Feng Liu

Oded Margalit

Robert J Baseman

Noam Slonim

Adam D Ticknor

Qi Liang

Raminderpal Singh

Fateh A Tipu

Ramona Kei

Michal Rosen-Zvi

Timothy M McCormack

Kevin MacKey

Jian Qiao Sun

Haizhou Yin

Katherine Lynn Saenger

Song Song

Kai Xiu

Weijun Wang

Hua Pin Shen

The present invention discloses a formation method, comprising: forming a hard mask layer and a photo-lithographic pattern of a fin structure on a the semiconductor substrate; patterning the hard mask layer and the semiconductor substrate to gain the fin structure with a profile of steep sidewalls; forming a protective layer on the sidewall surface of the fin structure; etching the semiconductor substrate located below the fin structure to form isolation structure trenches; performing a modified treatment on the exposed surfaces of the isolation structure trenches to form a modified layer with a certain thickness; removing the protective layer and the modified layer simultaneously; filling a dielectric layer in the isolation structure trenches till to cover the fin structure and then planarizing the dielectric layer; performing a trench etching to the dielectric layer and forming the fin structure and an isolation structure with sloped sidewalls.

Formation method of semiconductor structure

The present disclosure provides an image sensor and a method for manufacturing deep trench and through-silicon via of the image sensor, wherein: providing a pixel silicon wafer, performing a silicon wafer thinning on a second side of the pixel silicon wafer; forming a deep trench on the the second side of the pixel silicon wafer; filling the deep trench with organic material; coating photoresist on the second side of the pixel silicon wafer; etching the second side of the pixel silicon wafer to form a through-silicon via according to the through-silicon via pattern; depositing a dielectric protective layer on the surface of the deep trench and the surface of the through-silicon via; filling the deep trench with organic material; coating the photoresist on the second side of the pixel silicon wafer; etching the second side of the pixel silicon wafer to form a contact hole according to the contact hole pattern, depositing a barrier layer on the surface of the deep trench and the surface of the through-silicon via, filling the deep trench with a first metal, and form a seed layer on the surface of the through-silicon via; filling the through-silicon via with the first metal. The present disclosure reduces production steps of the image sensor.

Image sensor and method for manufacturing deep trench and through-silicon via of the image sensor

A method for hybrid wafer-to-wafer bonding, comprising: providing two silicon wafers with Cu pattern structures, a conventional Cu BEOL process is adopted on the silicon wafers to obtain the planarized surface with copper and dielectric; removing part of the Cu on the planarized surface of the Cu pattern structures by adopting an etching process to form a certain amount of Cu recesses; depositing a layer of bonding metal on the surface of the Cu by adopting a selective deposition process; performing surface activation on the bonding metal and the dielectric by adopting a surface activation process; aligning and pressing the two silicon wafers together to obtain the dielectric bonding; and obtaining the metal bonding through the annealing process. The sufficient metal bonding can be obtained at low annealing temperature according to the present invent, thereby the risk of dielectric delaminating caused by thermal expansion mismatch is reduced, which is conducive to reduce the difficulty of process integration, save process time and improve product yield.

Method for hybrid wafer-to-wafer bonding

A method for exposing polysilicon gate electrodes is disclose. The method comprises planarizing a pre-metal dielectric on a wafer surface; performing a selective etching process to the planarized pre-metal dielectric and a multi-layer dielectric which covers polysilicon gates in the wafer according to pre-set etching parameters to expose the polysilicon gates in the wafer. The selective etching process effectively control the amount of etching, which ensures high surface flatness when exposing the polysilicon gates without affecting the subsequent film deposition process. Therefore, wafer surface defects, gate stack damages, and polysilicon gate deformation caused by the conventional CMP process or the shear stress generated during the CMP process can be avoided, and then product yield can be enhanced.

Method for exposing polysilicon gates

A method for processing an electroplated copper film in copper interconnect process is disclosed by the present invention. Firstly, in the copper back-end-of-line interconnect process, the first annealing process for the electroplated copper film is performed at or below 180&#xb0; C.; then, after the copper back-end-of-line interconnect process, another annealing process with higher temperature (equal or above 240&#xb0; C.) to the electroplated copper film is performed to make the copper recrystallize, so as to decrease the resistivity of the electroplated copper film and form an interface state having lower resistivity at the interface of the vias bottom, which decrease the contact resistance between the vias and the underlying copper interconnects and further reduce the RC time delay in the vias. The present invention can be applied in the Cu/Low-k back-end-of-line interconnect process and compatible with the standard Cu/Low-k back-end-of-line process integration.

Method for processing an electroplated copper film in copper interconnect process

Processing instruction grouping information is provided that includes: reading addresses of machine instructions grouped by a processor at runtime from a buffer to form an address file; analyzing the address file to obtain grouping information of the machine instructions; converting the machine instructions in the address file into readable instructions; and obtaining grouping information of the readable instructions based on the grouping information of the machine instructions and the readable instructions resulted from conversion. Status of grouping and processing performed on instructions by a processor at runtime can be acquired dynamically, such that processing capability of the processor can be better utilized.

Code optimization based on information of readably converted executed instruction groups represented in address file

A method for control flow analysis according to an embodiment of the present invention includes: acquiring an original function call tree of a program, wherein nodes of the original function call tree represent functions and a parent/child relation between the nodes represents a calling relation; generating a corresponding function dominator tree from the calling relation, wherein nodes of the function dominator tree represent the functions and a parent/child relation between the nodes represents a dominator relation, wherein a first function dominates a second function if all the invocations to the second function are originated by the first function; and simplifying the original function call tree according to the function dominator tree so as to obtain a simplified function call tree. According to an embodiment of the present invention, the function call tree for control flow analysis can be simplified.

Control flow analysis utilizing function dominator trees

In one embodiment, a method comprises the steps of obtaining software architecture information for describing software architecture of the software; parsing the software architecture information to generate a set of module objects, wherein the module objects correspond to software modules of the software; obtaining a call object of the software call stack, wherein the call object corresponds to a method or function executed when the software is running; comparing an invocation interface of the module object with the call object; and associating corresponding information of the module object with the call object of the software call stack according to a comparison result.

Augmenting visualization of a call stack

A method, a system and a computer program product suitable for use in a manufacturing environment comprising a multiplicity of nominally identical independent tools. A computing device generates a multi dimensional array of process trace data derived from at least one of the independent tools, wherein, the array includes data representing a first dimension comprising a list of steps in a manufacturing recipe and data representing a second dimension comprising a list of a set of sensors generating measurements from at least one of the independent tools. The computing device conducts an analysis on at least one preselected subset of the multi dimensional array for the purpose of evaluating at least one operating characteristic of at least one of the independent tools. The computing device presents results of the analysis via a set of hierarchically linked and browseable graphics.

Method and system for evaluating a machine tool operating characteristics

A method and system for evaluating a performance of a semiconductor manufacturing tool while manufacturing microelectronic devices are disclosed. At least one report is generated based on executions of at least one statistical test. The report includes at least one heat map having rows that correspond to sensors, columns that correspond to trace data obtained during recipe steps, and cells at the intersection of the rows and the columns. At least one sensor in the tool obtains trace data of a recipe step while manufacturing at least one microelectronic device. A computing device analyzes the obtained trace data to determine a level of operational significance found in the data and assigns a score to the trace data that indicates a level of operational significance. Then, the computing device places the score in a corresponding cell of the heat map. A user uses the cell for evaluating the tool performance.

A semiconductor structure, such as a CMOS semiconductor structure, includes a field effect device that includes a plurality of source and drain regions that are asymmetric. Such a source region and drain region asymmetry is induced by fabricating the semiconductor structure using a semiconductor substrate that includes a horizontal plateau region contiguous with and adjoining a sloped incline region. Within the context of a CMOS semiconductor structure, such a semiconductor substrate allows for fabrication of a pFET and an nFET upon different crystallographic orientation semiconductor regions, while one of the pFET and the nFET (i.e., typically the pFET) has asymmetric source and drain regions.

Asymmetric source and drain field effect structure

The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices with stress-inducing structures located at the source and drain (S/D) regions. Specifically, each MOSFET comprises source and drain regions located in a semiconductor substrate. Such source and drain regions comprise recesses with one or more sidewall surfaces that are slanted in relation to an upper surface of the semiconductor substrate. A stress-inducing dielectric layer is located over the slanted sidewall surfaces of the recesses at the source and drain regions. Such MOSFETs can be readily formed by crystallographic etching of the semiconductor substrate to form the recesses with the slanted sidewall surfaces, followed by deposition of a stress-inducing dielectric layer thereover.

MOSFETS comprising source/drain recesses with slanted sidewall surfaces, and methods for fabricating the same

MOSFETs comprising source/drain recesses with slanted sidewall surfaces, and methods for fabricating the same

A user-oriented database query system, comprising user management means; device management means; control means for identifying a user, receiving a database query request and appended parameters, converting the database query request into a database query command; query agent means for submitting database query command at suitable time and receiving the query results; query recording means for storing the database query request, the appended parameters, the query command, the query time and the query results; wherein the control means further determines a receiving device, converts the query results into a form acceptable by the receiving device and sends the query results thereto, and terminates the query after the acknowledgment of the success of sending.

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Shanghai, China

Hong Lin