Siliconware Precision Industries Co., Ltd.

Hong-Da Chang

Shih-Kuang Chiu

Hsin-Yi Liao

Hsi-Chang Hsu

Yi-Che Lai

Chi-Ching Ho

Chi-Jen Chen

Chun-An Huang

Bo-Hao Ma

Cheng-Hsiang Liu

Chien-An Chen

Chen-Han Lin

Ching-Hung Tseng

Yu-Ting Xue

Chun-Chang Ting

Jun-Chang Ding

Guan-Hua Lu

Chun-Tang Lin

Chieh-Lung Lai

Hsien-Wen Chen

Chi-Hsin Chiu

Mao-Hua Yeh

Shih-Ching Chen

Hung-Wen Liu

Yi-Wei Liu

Chun-Hung Lin

Kuang-Wei Huang

A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.

Carrying substrate, electronic package having the carrying substrate, and methods for manufacturing the same

A method for fabricating an electronic package is provided. A filling material is formed in an interval S, at which a plurality of electronic components disposed on a carrying structure are spaced apart from one another. The filling material acts as a spacer having a groove, and the groove acts as a stress buffering region. Therefore, the electronic components can be prevented from being broken due to stress concentration.

Electronic package with multiple electronic components spaced apart by grooves

An electronic package, a packaging substrate, and methods for fabricating the same are disposed. The electronic package includes a circuit structure having a first side and a second side opposing the first side, an electronic component disposed on the first side of the circuit structure, an encapsulation layer formed on the first side of the circuit structure and encapsulating the electronic component, a metal structure disposed on the second side of the circuit structure, and a plurality of conductive elements disposed on the metal structure. The plurality of conductive elements are disposed on the metal structure, rather than disposed on the circuit structure directly. Therefore, the bonding between the conductive elements and the circuit structure is improved, to avoid the plurality of conductive elements from being peeled.

Electronic package, packaging substrate, and methods for fabricating the same

A semiconductor package and a method for fabricating the semiconductor package are provided. The semiconductor package includes a base layer, a plurality of conductive pillars, a semiconductor element, and an encapsulation. The base layer has opposing first and second surfaces and a receiving part. The conductive pillars are formed on the second surface. Each of the conductive pillars has first and second terminals, and the second terminal is distant from the second surface of the base layer. The semiconductor element is received in the receiving part, and has opposing active and passive surfaces, and the active surface is exposed from the first surface. The encapsulation is formed on the second surface, encapsulates the conductive pillars and the semiconductor element, and has opposing third and fourth surfaces, and the second terminals of the conductive pillars are exposed from the fourth surface. The semiconductor package is provided with the conductive pillars having fine pitches.

Semiconductor package having conductive pillars

A method for fabricating a package structure is provided, which includes: providing a first carrier having a circuit layer thereon; forming a plurality of conductive posts on the circuit layer and disposing at least an electronic element on the first carrier; forming an encapsulant on the first carrier to encapsulate the conductive posts, the circuit layer and the electronic element; and removing the first carrier, thereby dispensing with the conventional hole opening process for forming the conductive posts and hence reducing the fabrication costs.

Package structure and fabrication method thereof

A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a semiconductor structure having a carrier, a circuit portion formed on the carrier and a plurality of semiconductor elements disposed on the circuit portion; disposing a lamination member on the semiconductor elements; forming an insulating layer on the circuit portion for encapsulating the semiconductor elements; and removing the carrier. The lamination member increases the strength between adjacent semiconductor elements so as to overcome the conventional cracking problem caused by a CTE mismatch between the semiconductor elements and the insulating layer when the carrier is removed.

Semiconductor package and fabrication method thereof

A package structure is provided, which includes: a chip carrier having a plurality of conductive connection portions; at least an electronic element disposed on the chip carrier; a plurality of conductive wires erectly positioned on the conductive connection portions, respectively; an encapsulant formed on the chip carrier for encapsulating the conductive wires and the electronic element, wherein one ends of the conductive wires are exposed from the encapsulant; and a circuit layer formed on the encapsulant and electrically connected to exposed ends of the conductive wires. According to the present invention, the conductive wires serve as an interconnection structure. Since the wire diameter of the conductive wires is small and the pitch between the conductive wires can be minimized, the present invention reduces the size of the chip carrier and meets the miniaturization requirement.

Package structure and method for fabricating the same

A wafer level package having a pressure sensor and a fabrication method thereof are provided. A wafer having the pressure sensor is bonded to a lid, and electrical connecting pads are formed on the wafer. After the lid is cut, wire-bonding and packaging processes are performed. Ends of bonding wires are exposed and serve as an electrical connecting path. A bottom opening is formed on a bottom surface of the wafer, in order to form a pressure sensor path.

Fabrication method of wafer level package having a pressure sensor

A package structure is provided, which includes: a wafer having a surface with a groove, a thin film closing an open end of the groove and electrical contacts; a chip having a surface with a conductive layer and an opposite surface with a concave portion and a seal ring located at a periphery of the concave portion, the chip being disposed on the wafer with the seal ring surrounding the thin film and the electrical contacts located outside the seal ring; an encapsulant formed on the wafer for encapsulating the chip and the electrical contacts; a plurality of sub-conductive wires embedded in the encapsulant with one ends exposed from a top surface of the encapsulant and the other ends in electrical connection with the electrical contacts; and a through hole penetrating the wafer and communicating with the concave portion, thereby reducing the fabrication cost and size of the package structure.

Wafer level package having a pressure sensor and fabrication method thereof

A package structure is provided, including: a substrate having a ground pad and an MEMS element; a lid disposed on the substrate for covering the MEMS element; a wire segment electrically connected to the ground pad; an encapsulant encapsulating the lid and the wire segment; and a circuit layer formed on the encapsulant and electrically connected to the wire segment and the lid so as to commonly ground the substrate and the lid, thereby releasing accumulated electric charges on the lid so as to improve the reliability of the MEMS system and reduce the number of I/O connections.

Package structure having micro-electro-mechanical system element and method of fabrication the same

A fabrication method of a package structure having MEMS elements includes: disposing a plate on top of a wafer having MEMS elements and second alignment keys; cutting the plate to form therein a plurality of openings exposing the second alignment keys; performing a wire bonding process and disposing block bodies corresponding to the second alignment keys, respectively; forming an encapsulant and partially removing the encapsulant and the block bodies from the top of the encapsulant; and aligning through the second alignment keys so as to form on the encapsulant a plurality of metal traces. The present invention eliminates the need to form through holes in a silicon substrate as in the prior art so as to reduce the fabrication costs. Further, since the plate only covers the MEMS elements and the encapsulant is partially removed, the overall thickness and size of the package structure are reduced.

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Taichung, Taiwan

Hong-Da Chang