Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC Nanjing Company, Limited

Hong-Chen Cheng

Cheng Hung Lee

Hung-Jen Liao

Chih-Chieh Chiu

Chung-Ji Lu

Jung-Ping Yang

Chia-En Huang

Derek C Tao

Hsu-Shun Chen

Chung-Yi Wu

Jung-Hsuan Chen

Annie Lum

Vineet Kumar Agrawal

Keun-Young Kim

Pyong Yun Cho

Li-Chun Tien

Jonathan Tsung-Yung Chang

Fu-An Wu

Tsung-Hsien Huang

Yen-Huei Chen

Lee-Chung Lu

Hidehiro Fujiwara

Kuo-Hua Pan

Cheng-Hung Lee

I-Han Huang

Chun-Jiun Dai

Chung-Hsing Wang

Yun-Han Lee

Ching-Wei Wu

Chiting Cheng

Jui-Che Tsai

Tze-Chiang Huang

Annie-Li-Keow Lum

Wei-Pin Changchien

Ming-Yi Lee

Hsiao-Lan Yang

Chi-Kai Hsieh

Chien Chi Tien

Pei-Ying Lin

Shi-Wei Chang

Hsin-Wu Hsu

Jhon-Jhy Liaw

Wun-Jie Lin

Hau-Tai Shieh

Yangsyu Lin

Chien-Yuan Chen

Yi-Tzu Chen

Chia-Wei Wang

Wei-Jer Hsieh

You-Cheng Xiao

Chien-Chi Tien

Uppu Sharath Chandra

Hektor Huang

Yi-Hung Tsai

Wei-Shuo Kao

Lee Cheng Hung

Sang Hoo Dong

Ling-Chang Hu

Chung-Ji Liu

Lee-Cheng Hung

Ruei-Je Tsai

An integrated circuit (IC) die includes first through third adjacent rows of through-silicon vias (TSVs), and first and second adjacent rows of memory macros. TSVs of the first row of TSVs extend through and are electrically isolated from memory macros of the first row of memory macros. TSVs of the third row of TSVs extend through and are electrically isolated from memory macros of the second row of memory macros.

Integrated circuit die with memory macro including through-silicon via and method of forming the same

An integrated circuit (IC) package includes a logic die, a substrate, a memory die positioned between the logic die and the substrate, and a power distribution structure configured to electrically couple the logic die to the substrate. The power distribution structure includes a plurality of conductive segments positioned between the logic die and the memory die, a plurality of bump structures positioned between the memory die and the substrate, and a plurality of through-silicon vias (TSVs) electrically coupled to the plurality of conductive segments and the plurality of bump structures, and a TSV of the plurality of TSVs extends through, and is electrically isolated from, a memory macro of the memory die.

Memory macro including through-silicon via

A method of making a semiconductor device includes forming a first memory device, connecting a first word line to the first memory device, forming at least a first via, forming a second memory device, connecting a second word line to the second memory device, connecting a bit line to the first memory device and connecting the bit line to the second memory device by the first via. The first and second memory devices are separated by an inter-layer dielectric, and the first via connects the first memory device and the second memory device.

Semiconductor device having an inter-layer via (ILV), and method of making same

A memory macro structure includes a first memory array, a second memory array, a cell activation circuit coupled to the first and second memory arrays and positioned between the first and second memory arrays, a control circuit coupled to the cell activation circuit and positioned adjacent to the cell activation circuit, and a through-silicon via (TSV) extending through one of the cell activation circuit or the control circuit.

A method of fabricating an integrated circuit includes identifying an edge device of a plurality of devices, the plurality of devices being part of a first layout including gate structures and diffusion regions, modifying the first layout resulting in a second layout, and fabricating the integrated circuit based on the second layout. Modifying the first layout resulting in the second layout includes adding a dummy device next to the edge device, the dummy device and the edge device having a shared diffusion region, adding a dummy gate structure next to the dummy device, extending the shared diffusion region to at least the dummy device, and performing a design rule check on the second layout. The performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.

Method of fabricating a semiconductor device

A diagnostic system includes: a processor, arranged to extract a plurality of coordinates of a plurality of pins on an outer surface of a design layout according to a plurality of tagging texts labeling the plurality of pins respectively, and arranged to generate a design exchange format file according to the plurality of coordinates, wherein an order of the plurality of tagging texts are sorted by a predetermined scanning sequence; and a chip diagnostic tool, arranged to scan the plurality of scan components in a physical circuit on a testing platform through the plurality of pins on the outer surface of the physical circuit by following the predetermined scanning sequence to determine a defect component in the physical circuit according to the design exchange format file; wherein the physical circuit corresponds to the design layout.

System and method to diagnose integrated circuit

A method includes designing a first layout of gate structures and diffusion regions of a plurality of active devices, identifying an edge device of the plurality of active devices, modifying the first layout resulting in a second layout, performing a design rule check on the second layout, and fabricating, based on the second layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. Modifying the first layout includes adding a dummy device next to the edge device, adding a dummy gate structure next to the dummy device and extending a shared diffusion region to at least the dummy device. The dummy device and the edge device have the shared diffusion region. Performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.

A method includes designing a layout of gate structures and diffusion regions of a plurality of devices, identifying an edge device of the plurality of devices, adding a dummy device next to the edge device and a dummy gate structure next to the dummy device resulting in a modified layout, and fabricating, based on the modified layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. The dummy device shares a diffusion region with the edge device. A gate structure of the dummy device is one of two dummy gate structures added next to the edge device.

Modified design rules to improve device performance

A diagnostic system includes a location extractor, a file generator, and a chip diagnostic tool. The location extractor is arranged to extract at least a coordinate of at least one component in an intellectual property design layout of an integrated circuit design layout according to at least one tagging text labeling the at least one component in the intellectual property design layout. The file generator is arranged to generate a format file according to the at least coordinate. The chip diagnostic tool is arranged to scan a physical intellectual property circuit in a physical integrated circuit to determine a defect component in the physical intellectual property circuit according to the format file. The physical intellectual property circuit corresponds to the intellectual property design layout, and the physical integrated circuit corresponds to the integrated circuit design layout.

A three-dimensional integrated circuit includes a first transistor, a word line, a first via, a second transistor, and a second via. The first transistor is on a first level and the second transistor is on a second level. The second level is different from the first level. The word line and the first via are coupled to the first transistor. The second via is coupled between the first transistor and the second transistor.

Device having an inter-layer via (ILV), and method of making same

A memory includes a plurality of memory blocks, a plurality of sensing circuits, a plurality of global bit lines, a common pre-charging circuit and a selection circuit. Each global bit line of the plurality of global bit lines is coupled to at least one of the memory blocks by a corresponding sensing circuit of the plurality of sensing circuits. The common pre-charging circuit is configured to individually pre-charge each global bit line of the plurality of global bit lines to a pre-charge voltage. The selection circuit is configured to selectively couple the common pre-charging circuit to a selected global bit line of the plurality of global bit lines.

Memory and method of operating the same

A voltage providing circuit includes a first circuit configured to receive a first input signal and a second input signal and to generate an output signal. The first circuit includes a first transistor configured to switchably couple the second input signal to a first node responsive to the first input signal, a second transistor having a gate terminal coupled with the first node, and a third transistor having a source terminal coupled with a source terminal of the second transistor. The third transistor is configured to set a reference voltage value at the source terminal of the second transistor if the first input signal indicates that the second input signal is pulled from a first voltage value toward a second voltage value and if the second input signal reaches a predetermined voltage value. A second circuit is configured to receive the output signal and to generate an output voltage.

Voltage providing circuit

A method of designing a layout of devices includes designing a layout of gate structures and diffusion regions of a plurality of devices. The method further includes identifying an edge device of the plurality of devices. The method further includes adding a dummy device next to the edge device and a dummy gate structure next to the dummy device, wherein the dummy device shares a diffusion region with the edge device, and wherein a gate structure of the dummy device is considered to be one of two dummy gate structures added next to the edge device.

A signal generating circuit includes a first circuit, a tracking circuit, and a delay circuit. The delay circuit is coupled with the first circuit and the tracking circuit. The first circuit is configured to receive a first clock signal and an output signal from an output of the delay circuit, and to generate a second clock signal and at least one first tracking signal. The tracking circuit is configured to receive the at least one first tracking signal and to generate a second tracking signal. The delay circuit is configured to receive the second clock signal and the second tracking signal and to generate the output signal.

Tracking signals in memory write or read operation

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Hsinchu, Taiwan

Hong-Chen Cheng