Qualcomm Incorporated

Other

Hong Bok We

Aniket Patil

Dong Wook Kim

Jae Sik Lee

Kyu-Pyung Hwang

Joan Rey Villarba Buot

Young Kyu Song

Shiqun Gu

Kuiwon Kang

Chin-Kwan Kim

Jaehyun Yeon

Zhijie Wang

Suhyung Hwang

Kun Fang

Jonghae Kim

David Fraser Rae

Marcus Hsu

Brigham Navaja

Ratibor Radojcic

Michelle Yejin Kim

Jon Gregory Aday

Mohammad Ali Tassoudji

Milind Shah

Omar James Bchir

Nicholas Ian Buchan

Li-Sheng Weng

Manuel Aldrete

Charles David Paynter

Jie Fu

Urmi Ray

Jeahyeong Han

Steve Joseph Bezuk

Christopher Healy

Bohan Yan

Joonsuk Park

Durodami Lisk

Yuzhe Zhang

A package that includes a substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the substrate. The substrate includes at least one dielectric layer, and a plurality of interconnects comprising a plurality of escape interconnects. The plurality of escape interconnects includes a first embedded escape interconnect, a second embedded escape interconnect, and a third escape interconnect located between the first embedded escape interconnect and the second embedded escape interconnect.

Package with a substrate comprising embedded escape interconnects and surface escape interconnects

Integrated circuit (IC) packages employing wire bond channel over package substrate, and related fabrication methods. The IC package includes a first semiconductor die ('first die') and a first electronic device each coupled to a package substrate. To provide signal routing paths between the first die and the first electronic device, the IC package includes a wire bond channel that includes wire bonds coupled between first and second metal pads coupled to the respective first die and first electronic device to provide signal routing paths between the first die and first electronic device. The wire bonds extend outside of the package substrate in a vertical direction. The wire bond channel may be able to support more direct signal routing paths between the first die and the first electronic device without having to route such signal routing paths around a KoZ in the package substrate.

Integrated circuit (IC) packages employing wire bond channel over package substrate, and related fabrication methods

A device comprising a first package and a second package coupled to the first package through a first plurality of solder interconnects. The first package includes a first substrate comprising at least one first dielectric layer and a first plurality of interconnects, and a first integrated device coupled to the first substrate. The second package includes a second substrate comprising at least one second dielectric layer and a second plurality of interconnects, a second integrated device coupled to a first surface of the second substrate, a third integrated device coupled to the first surface of the second substrate through a second plurality of solder interconnects and a first plurality of channel interconnects coupled to the first surface of the second substrate, wherein the first plurality of channel interconnects is located between solder interconnects from the second plurality of solder interconnects.

Package comprising channel interconnects located between solder interconnects

Disclosed is a stack via structure in which a plurality of vias are stacked over each other. At least one via is a via that has a recess formed from a top surface thereof. Another via above the via is formed such that a bottom portion of the another via is in the recess of the via. In this way, no capture pad is needed between the via and the another via. Also, contact area between the via and the another via is enhanced.

Recess structure for padless stack via

Integrated circuit (IC) packages employing added metal for embedded metal traces in an ETS-based substrate for reduced signal path impedance. An IC package includes a package substrate and an ETS metallization layer disposed on the package substrate. To mitigate or offset an increase in impedance in longer signal paths between die circuitry and the package substrate that can result in decreased signaling speed and/or increased signal loss, added metal interconnects are coupled to embedded metal traces in the ETS metallization layer. Thus, embedded metal traces of the ETS metallization layer coupled to signal/ground signal paths of the die are increased in metal surface area. Increasing metal surface area of embedded metal traces coupled to the signal/ground signal paths of a die increases capacitance of such signal/ground signal paths. Increasing capacitance of signal/ground signal paths decreases impedance of the signal/ground signal paths to mitigate or reduce signaling delay and/or loss.

Integrated circuit (IC) package employing added metal for embedded metal traces in ETS-based substrate for reduced signal path impedance, and related fabrication methods

Disclosed are examples of integrated circuit (IC) packages. Each IC package may include a flip-chip (FC) die on a substrate, a wire bond die above the FC die, a wire bond connected to the wire bond die, and a mold on the substrate and encapsulating the FC die, the wire bond die, and the wire bond. The substrate may include least a first metallization layer includes a first substrate layer, a trace on the first substrate layer and routed within the first metallization layer to electrically couple with one or more FC interconnects of the FC die, and a bond finger pad formed on the trace. The bond finger pad may be circular. The wire bond may electrically connect to the trace such that the wire bond die is electrically coupled with the FC die through the wire bond, the bond finger pad, and the trace.

Circular bond finger pad

A package comprising an integrated device and a substrate. The integrated device is coupled to the substrate. The substrate includes a core layer, at least one first dielectric layer coupled to a first surface of the core layer, and at least one second dielectric layer coupled to a second surface of the core layer. The substrate includes a match structure located in the core layer. The match structure includes at least one first match interconnect extending vertically and horizontally in the match structure. The match structure also includes at least one second match interconnect extending vertically in the match structure. The at least one first match interconnect and the at least one second match interconnect are configured for skew matching.

Substrate comprising interconnects in a core layer configured for skew matching

Some features pertain to a hybrid package that includes a die, a first substrate structure, and a first metallization structure that is at least partially coplanar with the substrate. The die is electrically coupled to the first metallization structure and the first substrate through a second metallization structure. The first metallization structure is configured to provide an electrical path for data signaling. The second metallization structure is configured as a ground plane and is coupled to a ground signal. The first substrate structure is configured to provide an electrical path for power signaling.

Hybrid package apparatus and method of fabricating

Terminal connection routing on top of a substrate surface connects to component terminals to and from PMIC devices and provides a novel structure to connect surface mount technology (SMT) passive device terminals on an SMT layer (such as a Cu bar mesh) that uses the 3D space available near to components to lower resistance/lower inductive path and provides a shorter path, SIP form factor reduction, a component placement density increase, creates an additional PDN layer for connectivity and, if the routing is encapsulated in a mold, protects the metal in the connection from oxidation. Methods are presented for providing a substrate, attaching a first device to a first surface of the substrate near a center of the substrate, attaching a second device to the first surface of the substrate near an edge of the substrate, and connecting a connection located on the first surface of the substrate between the first device and the second device.

Terminal connection routing and method the same

A package comprising a substrate and an integrated device coupled to the substrate. The substrate comprises at least one dielectric layer; a plurality of interconnects comprising plurality of pad-on-pad interconnects, wherein the plurality of pad-on-pad interconnects is embedded through a first surface of the substrate. The plurality of pad-on-pad interconnects includes a first pad-on-pad interconnect comprising a first pad and a second pad coupled to the first pad. The package further comprising a solder resist layer located over the first surface of the substrate. The solder resist layer comprises a first solder resist layer portion comprising a first thickness; and a second solder resist layer portion comprising a second thickness that is less than the first thickness. The second solder resist layer portion is located between the at least one dielectric layer and the integrated device.

Package with a substrate comprising pad-on-pad interconnects

A semiconductor device includes a die having one or more trenches on a back side of the die. The semiconductor device also includes a layer of thermally conductive material deposited on the back side of the die to fill the one or more trenches to form one or more plated trenches. The size (e.g., surface area or thickness (Z-height)) or location of the plated trenches may be determined based on one or more heat generating elements such as logic devices (CPU or GPU, for example) on an active side of the die. The thermally conductive material, which may be a metal such as copper (Cu) or silver (Ag), has a heat dissipation coefficient that is greater than a heat dissipation coefficient of a substrate of the die.

Thermal mitigation die using back side etch

Multi-sided antenna modules employing antennas on multiple sides of a package substrate for enhanced antenna coverage, and related antenna module fabrication methods. The multi-sided antenna module includes an integrated circuit (IC) die(s) disposed on a first side of the package substrate. The multi-sided antenna module further includes first and second substrate antenna layers disposed on respective first and second sides of the package substrate. The first substrate antenna layer includes a first antenna(s) disposed on the first side of the package substrate adjacent to the IC die(s). The second substrate antenna layer includes a second antenna(s) disposed on the second side of the package substrate opposite of the first side of the package substrate. In this manner, the multi-sided antenna module, including antennas on multiple sides of the package substrate, provides antenna coverage that extends from both sides of the package substrate to provide multiple directions of coverage.

Multi-sided antenna module employing antennas on multiple sides of a package substrate for enhanced antenna coverage, and related fabrication methods

Integrated circuit (IC) packages employing a package substrate with a double side embedded trace substrate (ETS), and related fabrication methods. To facilitate providing a reduced thickness substrate in the IC package to reduce overall height of the IC package while supporting higher density input/output (I/O) connections, a package substrate in the IC package includes a double side ETS. A double side ETS includes two (2) adjacent ETS metallization layers that both include metal traces embedded in an insulating layer. The embedded metal traces in the ETS metallization layers of the double side ETS can be electrically coupled to each other through vertical interconnect accesses (vias) (e.g., metal pillars, metal posts) to provide signal routing paths between embedded metal traces in the ETS metallization layers.

Integrated circuit (IC) packages employing a package substrate with a double side embedded trace substrate (ETS), and related fabrication methods

A device comprising a first substrate comprising a first plurality of pillar interconnects; a second substrate comprising a second plurality of pillar interconnects, wherein the second plurality of pillar interconnects is coupled to the first plurality of pillar interconnects through a plurality of solder interconnects; a passive component located between the first substrate and the second substrate; and an integrated device coupled to the first substrate.

Package comprising passive component between substrates for improved power distribution network (PDN) performance

Examples herein include die to metallization structure connections that eliminate the solder joint to reduce the resistance and noise on the connection. In one example, a first die is attached to a metallization layer by a plurality of copper interconnections and a second is attached to the metallization layer opposite the first die through another plurality of copper interconnections. In this example, the copper interconnects may connect the respective die to a metallization structure in the metallization layer.

Growing community of inventors

San Diego, CA, United States of America

Hong Bok We