Tokyo Electron Limited

Université D'orleans

Hojin Kim

Soo Doo Chae

Shigeru Tahara

Jacques Faguet

Kaoru Maekawa

Lior Huli

Mingmei Wang

Du Zhang

Gaëlle Antoun

Remi Dussart

Thomas Tillocher

Philippe Lefaucheux

Karthikeyan Pillai

Na Young Bae

Stephen Mancini

In certain embodiments, a method of fabricating a device includes forming, on a substrate, a layer stack of alternating layers of a first spin-on material and a second spin-on material. Each layer of the first spin-on material and the second spin-on material is formed by spin-on deposition. The method includes etching first openings through the layer stack and filling the first openings with a third material. The method includes etching second openings through the layer stack, removing the first spin-on material from the layer stack, and replacing the first spin-on material with a fourth material. The fourth material is a first metal-containing material.

Fabricating three-dimensional semiconductor structures

A method for processing a substrate that includes: loading the substrate in a plasma processing chamber; performing a cyclic plasma etch process including a plurality of cycles, where each cycle of the plurality of cycles includes: generating a first plasma from a first gas mixture including a fluorosilane and oxygen; performing a deposition step by exposing the substrate to the first plasma to form a passivation film including silicon and fluorine; generating a second plasma from a second gas mixture including a noble gas; and performing an etch step by exposing the substrate to the second plasma.

Selective etching with fluorine, oxygen and noble gas containing plasmas

This disclosure describes a method for fabricating a plurality of semiconductor devices in a semiconductor wafer includes: bowing a semiconductor wafer including a substrate by covering the substrate with a strained layer; forming trenches at locations in scribe lines of the semiconductor wafer, the scribe lines identifying areas between adjacent dies on the semiconductor wafer; and reducing the bowing of the semiconductor wafer by filling the trenches with a stress-compensation material.

Stress relief in semiconductor wafers

Growing community of inventors

Albany, NY, United States of America

Hojin Kim