Qualcomm Incorporated

Inston, Inc.

University of California

Hochul Lee

Anil Chowdary Kota

Chulmin Jung

Dhvani Sheth

Albert Lee

Keejong Kim

Kang-Lung Wang

Seung Hyuk Kang

Chando Park

Bin Liang

Anne Srikanth

Kang L Wang

Arun Babu Pallerla

Pedram Khalili Amiri

Juan G Alzate

A memory is provided with a pair of banks including a first bank of bitcells and a second bank of bitcells. An I/O circuit for the pair of banks includes a shared write path configured to couple a write driver input signal to the first bank of bitcells responsive to an assertion of a write enable signal for the first bank of bitcells and to couple the write driver input signal to the second bank of bitcells responsive to an assertion of a write enable signal for the second bank of bitcells. The I/O circuit also includes a shared read path configured to couple a data bit output signal from the first bank of bitcells to a sense amplifier responsive to a de-assertion of the write enable signal for the first bank of bitcells and to couple a data bit output signal from the second bank of bitcells to the sense amplifier responsive to a de-assertion of the write enable signal for the second bank of bitcells. The shared read and write paths are further configured to operate simultaneously so that a write operation to one of the banks may occur while a read operation occurs to another one of the banks.

High-speed and area-efficient parallel-write-and-read memory

A memory is provided with a plurality of column groups and two redundant column groups. If there are two defective columns in the plurality of column groups, the plurality of column groups may be divided into a no-shift region, a one-shift region, and a two-shift region. The memory includes a plurality of input/output circuits corresponding to the plurality of column groups. Each input/output circuit may provide a data input signal during a write operation and receive a data output signal during a read operation. Each input/output circuit also includes a switch matrix. In the no-shift region, the switch matrix couples the input/output circuit to a core in the corresponding column group. In the one-shift region, the switch matrix couples the input/output circuit to a core in a subsequent column group. In the two-shift region, the switch matrix couples the input/output circuit to a core in a next-to-subsequent column group.

Memory with double redundancy

A memory is provided that includes a self-timed memory circuit that controls the isolation of a sense amplifier from a column selected by a column multiplexer until the completion of a bit line voltage difference development delay. The self-timed memory circuit also controls the release of a pre-charge for the sense amplifier responsive to the completion of the bit line voltage difference development delay.

Memory with a sense amplifier isolation scheme for enhancing memory read bandwidth

A memory is provided that includes multiple memory banks, each one of the memory banks being associated with a read multiplexer. A first read multiplexer couples a first plurality of bit lines to a first sense node pair, and a second read multiplexer couples a second plurality of bit lines to a second sense node pair. A first sense amplifier is coupled to the first sense node pair. The second sense node pair may be coupled to the same sense amplifier or a different sense amplifier.

Memory with reduced capacitance at a sense amplifier

A memory device with built-in flexible redundancy is provided according to various aspects of the present disclosure. In certain aspects, a memory device includes a first sense amplifier, a second sense amplifier, a first comparator, a second comparator, a reference circuit, and a logic gate. During a redundant read operation, the first sense amplifier, the first comparator, and the reference circuit are used to read one copy of a redundant bit stored in the memory device, and the second sense amplifier, the second comparator, and the reference circuit are used to read another copy of the redundant bit stored in the memory device. The logic gate may then determine a bit value based on the bit values of the read copies of the redundant bit (e.g., determine a bit value of one if the bit value of at least one of the read copies of the redundant bit is one).

Memory device with built-in flexible double redundancy

A memory is provided that includes a write multiplexer, which multiplexes among a plurality of bit line columns. The multiplexer includes a positive boost circuit that applies a positive boost to a voltage at the gates of transistors to strengthen an on state of those transistors. The positive boosting may be in addition to, or instead of, negative boosting at a write driver circuit.

Memory with positively boosted write multiplexer

An OTP memory cell circuit includes a read access switch coupled to a fuse in a read current path to allow a read current to flow through the fuse during a read operation. The read access switch, which can be shut off in a write operation, is sized according to the read current to reduce leakage currents that can cause unreliable results. A diode circuit coupled to a node between the read access switch and the fuse provides a write current path through the fuse different from the read current path in the OTP memory cell circuit. The diode circuit is configured to drive, through the write current path including the fuse, a write current sufficient to blow the fuse in a write operation. The diode circuit occupies a smaller area than a write access transistor of comparable drive strength in the OTP memory cell circuit.

One-time programmable (OTP) memory cell circuits employing a diode circuit for area reduction, and related OTP memory cell array circuits and methods

A memory device including: a first core of memory bitcells; a second core of memory bitcells; pre-decoding circuitry shared by the first core and the second core; and a row decoder coupled to the pre-decoding circuitry, the first core, and the second core, the row decoder including a first set-reset (SR) latch coupled to a first wordline of the first core and a second SR latch coupled to a second wordline of the second core.

Systems and methods for driving wordlines using set-reset latches

The present disclosure provides bit cells with data redundancy according to various aspects. In certain aspects, a bit cell includes a first memory element coupled to a write bit line, and a first write-access switch coupled between the first memory element and a ground. The bit cell also includes a second memory element coupled to the write bit line, and a second write-access switch coupled between the second memory element and the ground. The bit cell further includes a read-access switch coupled between the first memory element and a read bit line, wherein a control input of the read-access switch is coupled to a read-select line.

Bitcell for data redundancy

Certain aspects of the present disclosure provide methods and apparatus for testing a one-time programmable (OTP) memory device, including the functionality of a sense amplifier circuit. The OTP memory device includes a memory array, an input latch circuit, and a sense amplifier circuit comprising a current source and a multiplexer. The multiplexer has a first input coupled to an output of the memory array, a second input coupled to the input latch circuit, and an output coupled to an input of the current source circuit.

Testing one-time programmable (OTP) memory with data input capture through sense amplifier circuit

A One Time Programmable (OTP) memory, includes: a first driver coupled to a reference cell by a first bit line; a second driver coupled to an OTP cell by a second bit line; and a comparator having a first input coupled to the first bit line and the reference cell, a second input coupled to the second bit line and the OTP cell, and an output coupled to a logic circuit configured to control the first driver and the second driver.

Systems and methods to provide write termination for one time programmable memory cells

Systems and methods for reducing write error rate in MeRAM applications in accordance with various embodiments of the invention are illustrated. One embodiment includes a method for a writing mechanism for a magnetoelectric random access memory cell, the method including applying a voltage of a given polarity for a given period of time across a magnetoelectric junction bit of the magnetoelectric random access memory cell, wherein application of the voltage of the given polarity across the magnetoelectric junction bit reduces the perpendicular magnetic anisotropy and magnetic coercivity of the ferromagnetic free layer through a voltage controlled magnetic anisotropy effect, and lowering the applied voltage of the given polarity before the end of the given period of time, wherein the given period of time is approximately half of a precessional period of the ferromagnetic free layer.

Systems and methods for optimizing magnetic torque and pulse shaping for reducing write error rate in magnetoelectric random access memory

In certain aspects, a memory device includes memory bit cells coupled to a read bit line, and a first sense amplifier having a first input coupled to the read bit line, and a first output. The memory device also includes a latch amplifier having a first input coupled to the first output of the first sense amplifier, an enable input, and an output. The memory device also includes one or more dummy bit cells coupled to a dummy bit line, and a second sense amplifier having a first input coupled to the dummy bit line, and an output. The memory device further includes a trigger circuit having an input coupled to the output of the second sense amplifier, and an output coupled to the enable input of the latch amplifier.

Read tracking scheme for a memory device

Aspects of the disclosure provide magnetoresistive random access memory (MRAM) and methods. The MRAM generally includes a first magnetic tunnel junction (MTJ) storage element comprising a first fixed layer, a first insulating layer, and a first free layer, and a second MTJ storage element comprising a second fixed layer, a second insulating layer, and a second free layer. The MRAM further includes a conductive layer connected to a source line, first bit line, and a second bit line, wherein the first MTJ storage element is disposed above and connected to the conductive layer and the first bit line at a first end and connected to the first bit line at a second end, and wherein the second MTJ storage element is disposed above and connected to the conductive layer and the second bit line at a first end and connected to the second bit line at a second end.

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Los Angeles, CA, United States of America

Hochul Lee