Intel Corporation

Hoay Tien Teoh

Eng Huat Goh

Min Suet Lim

Jiun Hann Sir

Jenny Shio Yin Ong

Seok Ling Lim

Jia Yan Go

Jimmy Huat Since Huang

Tin Poay Chuah

Chin Lee Kuan

Mooi Ling Chang

Han Kung Chua

An electronic package with passive components located between a first substrate and a second substrate. The electronic package can include a first substrate including a device interface for communication with an electronic device. An interposer can be electrically coupled to the first substrate. A second substrate can be offset from the first substrate at a distance. The second substrate can be electrically coupled to the first substrate through the interposer. A passive component can be attached to one of the first substrate or the second substrate. The passive component can be located between the first substrate and the second substrate. A height of the passive component can be is less than the distance between the first substrate and the second substrate. The second substrate can include a die interface configured for communication with a die. The die interface can be communicatively coupled to the passive component.

Electronic package with passive component between substrates

A printed circuit board (PCB) comprises a blind via and a discrete component vertically embedded within the blind via.

Vertical embedded component in a printed circuit board blind hole

Donut-shaped Dynamic Random Access Memory (DRAM) includes a hole that fits around a processor, such that the DRAM and the processor are adjacent to one another on an Integrated Circuit (IC) package. In an embodiment, a heat spreader is mounted on top of the processor and covers a top of the DRAM without touching the DRAM.

Dynamic random access memory (DRAM) mounts

A jumper may be adapted to transmit an electrical signal. The jumper may be included in a system on a chip. The system on a chip may include a substrate, and the substrate may include one or more routing layers. The jumper may be included in the one or more routing layers of the substrate. A first interconnect may be positioned on a first side of the system on a chip, and a second interconnect may be positioned on a second side of the system on a chip. The jumper may be in electrical communication with the first interconnect, and may be in electrical communication with the second interconnect. The jumper may be electrically isolated from other components of the system on a chip, such as one or more die coupled to the substrate.

Package jumper interconnect

The electronic assembly includes a printed circuit board; an electronic package that includes an electronic component mounted on a substrate, wherein the substrate is mounted to the printed circuit board; a first memory module mounted to the printed circuit board such that the first memory module is adjacent to the electronic package; a second memory module mounted to the printed circuit board; and a substrate bridge that electrically connects the first and second memory modules to the electronic package, wherein a lower surface of the substrate bridge is connected to an upper surface of the substrate and an upper surface of the first and second memory modules.

Electronic assembly that includes a substrate bridge

Donut-shaped Dynamic Random Access Memory (DRAM) includes a hole that fits around a processor, such that the DRAM and the processor are adjacent to one another on an Integrated Circuit (TC) package. In an embodiment, a heat spreader is mounted on top of the processor and covers a top of the DRAM without touching the DRAM.

Interconnects for semiconductor packages are described. An apparatus may comprise a decoupling capacitor on a logic board, and a conductive interconnect element on the logic board, the conductive interconnect element to connect the decoupling capacitor on the logic board to a power conductor comprising a power pad of a semiconductor package, the conductive interconnect element at a different layer than a ground-potential layer of the logic board. Other embodiments are described and claimed.

Interconnects for semiconductor packages

Described herein are integrated circuit structures having a package substrate with microstrip architecture as the uppermost layers and a surface conductive layer that is electrically connected to a ground plane internal to the package substrate, as well as related devices and methods. In one aspect of the present disclosure, an integrated circuit package substrate may have an internal ground plane, a dielectric layer, a microstrip signal layer as the top transmission line layer, a solder resist layer, and a surface conductive layer that is electrically connected to the internal ground plane in the package substrate. In another aspect of the present disclosure, an integrated circuit package substrate may include altering thicknesses of the dielectric and/or solder resist layers to optimize electrical performance by having the microstrip signal layer closer in proximity to the internal ground layer as compared to the surface conductive layer.

Integrated circuit package substrate with microstrip architecture and electrically grounded surface conductive layer

A three capacitor stack and associated methods are shown. An exemplary capacitor device may include a first capacitor stack that includes a first plurality of layers of reference electrodes interleaved with first capacitor electrodes, a second capacitor stack on the first capacitor stack that includes a second plurality of layers of reference electrodes interleaved with second capacitor electrodes, and a third capacitor stack on the second capacitor stack that includes a reference electrode and a third capacitor electrode. A respective layer of dielectric material is formed between the reference electrodes and the first capacitor electrodes, the second capacitor electrodes, and the third capacitor electrode.

Three capacitor stack and associated methods

A computer system assembly that includes a substrate and a first board mounted on the substrate. A flexible cable is secured to the first board. The computer system assembly further includes a second board mounted on the substrate. The second board includes a FPC connector. The FPC connector includes a body having a channel extending through the body such that the flexible cable may be positioned in the channel and pulled entirely through the body of the FPC connector. The FPC connector further includes a latching mechanism that secures the flexible cable within the channel once the flexible cable is pulled through the FPC connector. The first board and the second board are moved closer together as the flex cable is pulled through the FPC connector before at least one of the first board and the second board is mounted on the substrate.

FPC connector for better signal integrity and design compaction

A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second bumpless build-up layer structure adjacent a back surface of the microelectronic device, wherein conductive routes are formed through the first bumpless build-up layer from the microelectronic device active surface to conductive routes in the second bumpless build-up layer structure and wherein through-silicon vias adjacent the microelectronic device back surface and extending into the microelectronic device are electrically connected to the second bumpless build-up layer structure conductive routes.

Growing community of inventors

Paya Terubong, Malaysia

Hoay Tien Teoh