Nec Corporation

Sony Corporation

Hitoshi Wakabayashi

Satoru Mayuzumi

Shigeharu Yamagami

Kiyoshi Takeuchi

Koichi Takeda

Masahiro Nomura

Masayasu Tanaka

Koichi Terashima

Toru Tatsumi

Atsushi Ogura

Risho Koh

Yukishige Saito

Koji Watanabe

Katsuhiko Tanaka

Tohru Mogami

Hiroyuki Nakamura

Takashi Ishigami

Hisashi Takemura

Tadahiko Horiuchi

Toshitada Doi

Koichiro Okumura

Yukinori Ochiai

Yoshifumi Okuda

Yoshiaki Kikuchi

Mitsuru Narihiro

Toyoji Yamamoto

Jong-Wook Lee

Kohichi Arai

Takemitsu Kunio

A semiconductor device including a channel region formed in a semiconductor substrate; a source region formed on one side of the channel region; a drain region formed on the other side of the channel region; a gate electrode formed on the channel region with a gate insulating film therebetween; and a stress-introducing layer that applies stress to the channel region, the semiconductor device having a stress distribution in which source region-side and drain region-side peaks are positioned between a pn junction boundary of the channel region and the source region and a pn junction boundary of the channel region and the drain region.

Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions

A semiconductor device including a channel region formed in a semiconductor substrate; a source region formed on one side of the channel region; a drain region formed on the other side of the channel region; a gate electrode formed on the channel region via a gate insulating film; and a stress-introducing layer that applies stress to the channel region, the semiconductor device having a stress distribution in which source region-side and drain region-side peaks are positioned between a pn junction boundary of the channel region and the source region and a pn junction boundary of the channel region and the drain region.

A semiconductor device includes: a channel region formed in a semiconductor substrate; a source region formed on one side of the channel region; a drain region formed on the other side of the channel region; a gate electrode formed on the channel region via a gate insulating film; and a stress-introducing layer that applies stress to the channel region, the semiconductor device having a stress distribution in which source region-side and drain region-side peaks are positioned between a pn junction boundary of the channel region and the source region and a pn junction boundary of the channel region and the drain region.

Semiconductor device having a stress-inducing layer between channel region and source and drain regions

A semiconductor device includes: a semiconductor substrate in which a SiGe layer having a first width in a channel direction is embedded in a channel forming region; gate insulating film formed on the channel forming region; a gate electrode formed on the gate insulating film and having a region protruding from a forming region of the SiGe layer with a second width wider than the first width; and source/drain regions having extension regions formed on the semiconductor substrate which sandwiches the channel forming region, thereby forming a field effect transistor, wherein the extension region is apart from the SiGe layer so that a depletion layer extending from a junction surface between the extension region and the semiconductor substrate does not reach the SiGe layer.

Semiconductor device with field effect transistor and manufacturing method thereof

A semiconductor device having SRAM cell units each comprising a pair of a first driving transistor and a second driving transistor, a pair of a first load transistor and a second load transistor, and a pair of a first access transistor and a second access transistor, wherein each of the transistors comprises a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulating film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; and the first and second driving transistors each have a channel width larger than that of at least either each of the load transistors or each of the access transistors.

Semiconductor device and manufacturing method thereof

The present invention provides a semiconductor device and a method of manufacturing a semiconductor device in which a driving force can be increased by increasing a strain amount given by a stressed film in a MOS transistor including an elevated region. On a silicon substrate, a device isolation region, a gate insulating film, a gate electrode, an extension, and a sidewall insulating filmare formed. After that, an elevated region is formed, and a source/drain regionand a silicide layerare formed. Subsequently, the sidewall insulating filmis etched to provide a gap from the elevated region, and a stressed filmis buried in the gap.

Semiconductor device and method of manufacturing semiconductor device

The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor layer, and source and drain regions provided in the protrusive semiconductor layer, wherein the semiconductor device has on a semiconductor substrate an element forming region having a Fin type FET, a trench provided on the semiconductor substrate for separating the element forming region from another element forming region, and an element isolation insulating film in the trench; the element forming region has a shallow substrate flat surface formed by digging to a depth shallower than the bottom surface of the trench and deeper than the upper surface of the semiconductor substrate, a semiconductor raised portion protruding from the substrate flat surface and formed of a part of the semiconductor substrate, and an insulating film on the shallow substrate flat surface; and the protrusive semiconductor layer of the Fin type FET is formed of a portion protruding from the insulating film of the semiconductor raised portion.

Semiconductor device with fin-type field effect transistor and manufacturing method thereof.

A semiconductor device comprising a first semiconductor region and a second semiconductor region,

Semiconductor device and method for manufacturing same

A semiconductor device comprising: a MIS type field effect transistor which comprises a semiconductor raised portion protruding from a substrate plane, a gate electrode extending over the semiconductor raised portion from the top onto the opposite side faces of the semiconductor raised portion, a gate insulation film existing between the gate electrode and the semiconductor raised portion, and source and drain regions provided in the semiconductor raised portion; an interlayer insulating film provided on a substrate including the transistor; and a buried conductor interconnect that is formed by filling in a trench formed in the interlayer insulating film with a conductor, wherein the buried conductor interconnect connects one of the source and drain regions of the semiconductor raised portion and another conductive portion below the interlayer insulating film.

Semiconductor device having a conductive portion below an interlayer insulating film and method for producing the same

A semiconductor device includes a semiconductor layer formed on an insulator, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film and extending in a first direction, source/drain regions formed in the semiconductor layer on both sides of the gate electrode, a body contact region in the semiconductor layer, a partial isolating region in which a field insulating film thicker than the gate insulating film intervenes between the semiconductor layer and an extending portion of the gate electrode, and a full isolating region in which the semiconductor layer on the insulator is removed. The full isolating region is formed to be in contact with at least a part of a side parallel to the first direction of the source/drain regions.

SOI MOSFET

One object of the present invention is to suppress a threshold voltage of at least an n-channel MISFET using a nitride of a high melting point metal at it's gate electrode. In order to achieve the object, a gate electrodeof a p-channel MISFET is constituted of a titanium nitride filmand a tungsten filmformed on the filmand a gate electrodeof an n-channel MISFET is constituted of a titanium nitride filmand a tungsten filmformed on the film. The titanium nitride filmis formed by nitrogen ion implantation in the titanium nitride filmto decrease the work function.

Growing community of inventors

Tokyo, Japan

Hitoshi Wakabayashi