Nec Corporation

Nec Electronics Corporation

Hitoshi Abiko

Minoru Higuchi

Ken Inoue

Isami Sakai

Nobuyuki Katsuki

Hirofumi Nikaido

Yasuhiro Kawakatsu

Michihiro Kobayashi

A lower electrode projects outward from a common end face of an upper electrode and a capacitor film. A protective film, which is made of a different material from the capacitor film, is deposited on top of a part of the lower electrode outside the end face. The protective film also extends to the position at a certain distance inward from the end face, so that it is placed between the capacitor film and the lower electrode. The capacitor film thereby has a stepped surface near the end face due to the presence of the protective film, which suppresses the progress of damage during etching of the upper electrode and the capacitor film. Further, the protective film prevents the occurrence of damage in the lower electrode.

Semiconductor device

A backside imaging device includes a bump that is disposed overlapping with a sensor array region or a photodiode in a planar view. By this configuration, the bump becomes a support, and the semiconductor substrate is prevented from being damaged because of a bending applied to the semiconductor substrate.

Imaging device

In a memory cell area (A) of a semiconductor storage device, a capacitor ( ) formed on a first insulating layer ( ) formed so as to cover MOS transistors ( ) includes a pillar-shaped insulating member ( ), a first capacitance electrode ( ) formed on the side surface of the pillar-shaped insulating member ( ), a capacitance insulating film ( ) formed on the first capacitance electrode ( ) and a second capacitance electrode ( ) formed on the capacitance insulating film ( ). A conductive member ( ) for connecting the source or drain ( ) of the MOS transistor ( ) to the first capacitance electrode ( ) is filled in a connection opening ( ) formed in the first insulating layer ( ). In a peripheral circuit area (B) other than the memory cell area (A) containing plural memory cells each having the MOS transistor ( ) and the capacitor ( ), a second insulating layer ( ) which is formed simultaneously with the formation of the pillar-shaped insulating member ( ) of the capacitor ( ) and has the same height as the pillar-shaped insulating member ( ) is formed on the first insulating layer ( ).

Semiconductor memory cell device

A metal gate MISFET comprises a metal gate electrode on a semiconductor substrate, a side wall insulation film, and a source-drain region which is formed on the surface of the semiconductor substrate on both sides of the side wall insulation film. Then, a cobalt silicide film is formed on the source-drain region. In this step of manufacturing the MISFET, since the cobalt silicide film is sealed with the silicon nitride film at the time of oxidizing the surface of the substrate of a gate portion, the property of the cobalt silicide film will never be deteriorated. As a consequence, the metal-gate field effect transistor having a low parasitic resistance of the source-drain region can be obtained.

Metal-gate field effect transistor and method for manufacturing the same

There is provided a method for manufacturing a semiconductor device for forming a silicide layer of metal of high melting point, wherein the metal of high melting point is processed in sputtering under a condition in which no deterioration is produced by the sputtering apparatus. There is also provided a sputtering apparatus for manufacturing semiconductor device. In the method of the present invention, a high melting point metal is accumulated on a silicon substrate formed with a gate electrode of a semiconductor element to form a metallic film of high melting point, thereafter it is heat treated to form a silicide layer of the high melting point metal at an interface layer with the metallic film with high melting point, and in this case, the metallic film of high melting point is accumulated in sputtering by a magnetron sputtering device under a condition in which an electrical load amount Q reaching to the gate electrode is less than 5 C/cm,. In addition, the sputtering apparatus,has the collimator plate,including an electrical conductive material having many through-pass holes passed from the target toward the wafer between the target holder,and the wafer holder,while it is being connected to an earth terminal.

Sputtering apparatus for sputtering high melting point metal and method for manufacturing semiconductor device having high melting point metal

In a method of fabricating a semiconductor device by the use of a semiconductor substrate (,), boron ions (,) are implanted into the semiconductor substrate from a trench (,) which is formed to the semiconductor substrate. The trench is defined by a plurality of side surfaces and a bottom surface extending between the side surfaces. The boron ions are implanted through all of the side surfaces and the bottom surface. It is preferable that isolating material is filled into the trench to produce a trench isolation extending over a p-well (,) and a n-well (,).

Method of fabricating semiconductor device capable of providing MOSFET which is improved in a threshold voltage thereof

A semiconductor device of the present invention and using trench isolation includes contact holes. Spacers are formed on the shoulder portions of a device region exposed in the contact holes. To form the spacers, a silicon oxide film is formed and then etched by anisotropic etching such that the film does not fill up the contact holes. The anisotropic etching may be effected after oxidation. With this structure, it is possible to prevent junction leakage current from increasing.

Semiconductor device and method of producing the same

To form a device isolating deep trench adjacent to a well, the deep trench is formed by using, as a mask, a photoresist mask used for forming the well and a silicon oxide film or a polysilicon film formed on a semiconductor substrate and patterned by an etching using another photoresist mask which was used for forming an adjacent well, or two patterned insulating layers formed on the semiconductor substrate. Thus, the deep trench for the device isolation can be formed without adding a photoresist step for forming a trench formation pattern. In addition, since a lift-off process is not used for forming the deep trench, an isolation trench having a narrow width can be formed, and also, there does not occur the re-deposition of the peeled-off plasma CVD insulating film onto the semiconductor substrate, with the result that the stability in manufacturing the semiconductor device is remarkably elevated.

Method for manufacturing semiconductor device

A semiconductor device having a CMOS structure having a low resistivity silicide layer in a source/drain region is fabricated. To realize silicide formation for resistivity reduction of the n-type source/drain region, an impurity-free silicon layer is formed thereon before forming a high melting point metal silicide layer. For the n-type source/drain region, ion implantation is made through the silicon layer. It is thus possible to obtain a shallow junction of the p-type source/drain region, prevent ion implantation time increase and obtain quick fabrication without reducing the ion implantation energy.

Method for fabricating semiconductor device having CMOS structure

When an isolating oxide is formed in a silicon substrate, a side wall is formed on the inner wall of a mask consisting of a lower silicon oxide layer and an upper silicon nitride layer for forming a groove in the silicon substrate in such a manner as to be laterally spaced from the inner wall of the upper silicon nitride layer, and the isolating oxide is formed from a silicon oxide layer deposited over the mask after removal of the side wall by using a polishing, thereby preventing the isolating oxide from undesirable side etching during an etching step for the lower silicon oxide layer.

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Tokyo, Japan

Hitoshi Abiko