Seiko Instruments Inc

Silterra Malaysia Sdn. Bhd.

Hitomi Watanabe

Naoto Inoue

Min Paek

Sang Yeon Kim

Inki Kim

Wan Gie Lee

Choong Shiau Chien

Chiew Sin Ping

Zadig Lam

Charlie Tay

Chang Gi Lee

Ch'ng Toh Ghee

Ramakrishnan Rajagopal

Hiroaki Takasu

Yutaka Saito

Masaaki Kamiya

Kazutoshi Ishii

Toshihiko Omi

Naoto Saitoh

Takao Akiba

Koju Nonaka

Chiew Gie Lee

A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact. Thereafter, a first gate oxide having a first thickness is formed on the first active region, the first gate oxide having a first edge facing the first isolation structure and a second edge facing the second isolation structure. The first edge is separated from the first isolation structure by a first distance. The second edge is separated from the second isolation structure by a second distance. Thereafter, a second gate oxide having a second thickness is formed on the second active region, the second thickness being different than the first thickness.

Semiconductor device with dual gate oxides

A method for forming an isolation structure on a semiconductor substrate includes opening a portion of a pad oxide layer overlying the substrate using a process gas including an etchant gas and a polymer-forming gas. A portion of the substrate exposed by the opening step is etched to form a trench having a first slope and a second slope. The first slope is greater than 45 degrees, and the second slope is less than 45 degrees. The trench is filled to form the isolation structure.

Shallow trench isolation

An N-channel MOS transistor of a semiconductor device having a high withstand voltage employs a drain structure with a low concentration and a large diffusion depth, which causes a problem in that a sufficiently high withstand voltage cannot be obtained due to a parasitic NPN transistor formed among the drain, the well, and the semiconductor substrate which are arranged in the stated order. According to the present invention, provided are a semiconductor device, including: a semiconductor substrate; an epitaxial layer having an electric polarity identical with that of the semiconductor substrate, which is formed on the semiconductor substrate; a buried diffusion layer having the electric polarity different from that of the semiconductor substrate, which is formed between the semiconductor substrate and the epitaxial layer; and a well region having the electric polarity identical with that of the buried diffusion layer, which is formed above the buried diffusion layer and is electrically connected therewith, in which a MOS transistor is formed in a well having a structure in which the buried diffusion layer is electrically connected with the well region, and a manufacturing method therefor.

Semiconductor integrated circuit device having MOS transistor

In a method for manufacturing a semiconductor device, a first silicon oxide film is formed on a semiconductor substrate. The first silicon oxide film is nitrided so that silicon oxynitride forms at an interface between the semiconductor substrate and the first silicon oxide film. The first silicon oxide film is removed from a portion of the semiconductor substrate using a chemical containing at least an ammonia-hydrogen peroxide solution so that the silicon oxynitride formed at the interface between the portion of the semiconductor substrate and the first silicon oxide film is completely removed. Thereafter, a second silicon oxide film is formed in the portion of the semiconductor substrate from which the first silicon oxide film and the silicon oxynitride have been removed.

Manufacturing method for a semiconductor device

A method for manufacturing a semiconductor device comprises the steps of forming a gate oxide film on a surface of a semiconductor substrate, subjecting the gate oxide film to a nitriding treatment, forming a gate electrode film over the surface of the semiconductor substrate, annealing the gate oxide film in an inert gas atmosphere after the nitriding treatment and after formation of the gate electrode film, and thereafter patterning the gate electrode film to form a gate electrode.

Method for manufacturing semiconductor device

In the fabrication of a MOS transistor, a single process step is performed for controlling the threshold voltage of the transistor and improving the reliability of a gate insulating film so that the number of manufacturing steps is decreased. A desired amount of fixed electric charge is provided at an interface between a semiconductor substrate and the gate insulating film by a nitriding process performed on the gate insulating film to form a channel region and control the threshold voltage of the MOS transistor, so that both an improvement in the reliability of the gate insulating film and control of the threshold voltage of the MOS transistor are performed in one step.

Method of manufacturing a semiconductor device having nitrogen ions by twice RTA processes

An EEPROM cell having one layer of polycrystalline silicon in which a memory cell area is reduced without damaging cell characteristics by providing a channel length of a select gate transistor and a channel length of a cell transistor to extend perpendicularly to each other, and that a select gate electrode and a control gate electrode of an impurity diffusion layer are arranged in parallel with each other, and a cell source wiring is made of a metal wiring through a contact, so that a parasitic transistor on the control gate wiring is eliminated and it becomes possible to effectively reduce the cell area.

EEPROM cell having reduced cell area

In a semiconductor manufacturing process for a semiconductor device having two layers of polycrystalline silicon and a Double Diffused Drain (DDD) type transistor, the number of heat treatment processes is minimized to avoid degrading the quality of a gate oxide film, such as a tunnel oxide film in an EEPROM. After forming a gate electrode of a DDD transistor and a lower electrode of a capacitor, for example, of a first polycrystalline silicon film, a DDD impurity diffusion region is formed by a heat treatment process combined with a thermal oxide growth process for producing an oxide dielectric for the capacitor and a gate oxide of a peripheral transistor. A second polycrystalline silicon film is then formed as a gate electrode of the peripheral transistor and an upper electrode of the capacitor, thereby reducing the number of process steps and improving the quality of the gate oxide film and a tunnel oxide film by reducing the length of the heat treatment processes.

Method of producing semiconductor having two-layer polycrystalline silicon structure

The present invention is provided for improving latch-up resistance in a semiconductor integrated circuit device employing CMOS structure, for preventing the photoelectric carriers from getting into the sensors and improving the afterimage characteristic in a semiconductor image sensor device, and for impurity the switching characteristic in a semiconductor device having bipolar element. An electron beam of over 2 MeV and 1E15/cm.sup.2 is irradiated to a monocrystal silicon semiconductor region in a substrate and then annealing is performed at a high temperature of over 200.degree. C. As a result, at 150 K., a shallow level traps of which the activation energy from a valence band EV is under 0.1 eV and which is produced at the concentration of about 1.2-1.7E15/cm.sup.3, and a deep level traps of which the activation energy is 0.28-0.32 eV and which is produced at the concentration of about 1.6-2.0E13/cm.sup.3 are obtained. Then a semiconductor substrate having both the level traps stated above as recombination centers in a band gap of silicon is obtained. The chip size of this semiconductor substrate doesn't increase, and furthermore the cost of it is low as an epi wafer is not used. As well, it is possible to manufacture a semiconductor integrated circuit device just before or just after a process step of evaluating the electrical characteristic of a semiconductor integrated circuit device.

Semiconductor device having defects of deep level generated by electron

A semiconductor device comprises a silicon semiconductor substrate and an insulating film formed on a surface of the silicon semiconductor substrate. One of a surface of the silicon semiconductor substrate or a surface of the insulating film is provided with at least one step portion. A polycrystalline silicon layer is formed uniformly on at least a side surface of the step portion and a top surface of the insulating film. The polycrystalline silicon layer which is formed on the side surface of the step portion comprises a resistance element, and a portion of the polycrystalline silicon layer which is formed on the top surface of the insulating film is doped with an impurity to form a conductive element. By this construction, the area occupied by the load devices on the semiconductor substrate is effectively reduced, thereby increasing the packing density of the semiconductor device.

Growing community of inventors

Chiba, Japan

Hitomi Watanabe