Sandisk 3d LLC

Sandisk Technologies Inc.

Hitomi Fujimoto

Hiroaki Iuchi

Chao Feng Yeh

Ming Tian

Hisayuki Nozawa

Daisuke Maekawa

Electrical isolation in non-volatile memory is provided by air gaps formed using sacrificial films of differing etch rates. A high etch rate material is formed in an isolation trench. Flowable chemical vapor deposition processes are used to form high etch rate films, and curing is performed to increase their etch rate. A low etch material is formed over the high etch rate material and provides a controlled etch back between charge storage regions in a row direction. A discrete low etch rate layer can be formed or the high etch rate material can be oxidized to form an upper region with a lower etch rate. A controlled etch back enables formation of a wrap-around dielectric and control gate structure in the row direction with minimized variability in the dimensions of the structures. At least a portion of the high etch rate material is removed to form air gaps for isolation.

Air gap isolation in non-volatile memory using sacrificial films

Techniques disclosed herein may achieve crack free filling of structures. A flowable film may substantially fill gaps in a structure and extend over a base in an open area adjacent to the structure. The top surface of the flowable film in the open area may slope down and may be lower than top surfaces of the structure. A capping layer having compressive stress may be formed over the flowable film. The bottom surface of the capping layer in the open area adjacent to the structure is lower than the top surfaces of the lines and may be formed on the downward slope of the flowable film. The flowable film is cured after forming the capping layer, which increases tensile stress of the flowable film. The compressive stress of the capping layer counteracts the tensile stress of the flowable film, which may prevent a crack from forming in the base.

Method of forming crack free gap fill

Techniques disclosed herein prevent wire flaking (collapse). One aspect is an improved way of forming wires over trenches, which may be located in a hookup region of a 3D memory array, and may be used to form electrical connections between conductive lines in the memory array and drivers. The trenches are formed between CMP dummy structures. The trenches are partially filled with a flowable oxide film, which leaves a gap in the trench that is at least as wide as the total pitch of the wires to be formed. A capping layer is formed over the flowable film. After forming a conductive layer over the dielectric layer, the conductive layer is etched to form conductive wires. Some of the capping layer, as well as the CMP dummy structures may be removed. Thus, the conductive wires may be at least temporarily supported by lines of material formed from the capping layer.

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Yokkaichi, Japan

Hitomi Fujimoto