Kabushiki Kaisha Toshiba

Other

Tokyo Electron Limited

Ibiden Company Limited

Ebara Corporation

Hisashi Kaneko

Tetsuo Matsuda

Masahiko Hasunuma

Nobuo Hayasaka

Hiroshi Toyoda

Junichi Wada

Katsuya Okumura

Akihiro Kajita

Takamasa Usui

Sachiyo Ito

Hideki Shibata

Takashi Kawanoue

Atsuko Sakata

Kazuyuki Higashi

Noriaki Matsunaga

Koji Mishima

Hirokazu Ezawa

Haruo Okano

Junji Kunisawa

Mie Matsuo

Tadashi Iijima

Tomio Katata

Kenji Yoshida

Natsuki Makino

Kenji Nakamura

Hiroaki Inoue

Kiyoshi Takekoshi

Junichi Hagihara

Takeshi Nishioka

Masaaki Hatano

Hisatomi Hosaka

Toshiyuki Morita

Motoya Okazaki

Yoshiyuki Ido

Kunihiko Hatsushika

Hiroshi Tomita

Norio Kimura

Kyoichi Suguro

Hiroyuki Yano

Makoto Honda

Takashi Kawakubo

Gaku Minamihaba

Naofumi Nakamura

Manabu Tsujimura

Rempei Nakata

Atsuhito Sawabe

Yasutaka Sasaki

Dai Fukushima

Hideaki Hirabayashi

Shuichi Komatsu

Tadashi Matsuno

Minakshisundaran Balasubramanian Anand

Mitsuhiro Nakao

Hideaki Harakawa

Hideto Matsuyama

Koji Miyamoto

Masanori Numano

Keizo Shimamura

Jun-ichi Wada

Takahito Nagamatsu

Takeshi Fujimaki

Toshiaki Komukai

Mitsuko Odagaki

Junsei Tsutsumi

Masami Miyauchi

Shohei Shima

Yoshiko Kohanawa

Soichi Inoue

Hideo Aoki

Ichiro Omura

Kenji Takahashi

Yuichiro Yamazaki

Chiaki Takubo

Motosuke Miyoshi

Mizuki Nagai

Hideshi Miyajima

Mitsuhiro Omura

Masami Aoki

Makoto Sekine

Hiroko Nakamura

Kenichi Matsushita

Hideo Numata

Yoshikuni Tateyama

Shoko Ito

Osamu Nagano

Sachiko Kobayashi

Kazuko Yamamoto

Seiichi Omoto

Soichi Yamashita

Tadayoshi Watanabe

Takashi Yoda

Jun Hirota

Ryoichi Kimizuka

Takaya Matsushita

Susumu Harada

Makiko Katano

Yutaka Nakano

Masatoshi Higuchi

Hiroyuki Toshima

Hideo Shinomiya

A reliability evaluation test apparatus of this invention includes a wafer storage section which stores a wafer in a state wherein the electrode pads of a number of devices formed on the wafer and the bumps of a contactor are totally in electrical contact with each other. The wafer storage section transmits/receives a test signal to/from a measurement section and has a hermetic and heat insulating structure. The wafer storage section has a pressure mechanism which presses the contactor and a heating mechanism which directly heats the wafer totally in contact with the contactor to a predetermined high temperature. The reliability of an interconnection film and insulating film formed on the semiconductor wafer are evaluated under an accelerated condition.

Reliability evaluation test apparatus, reliability evaluation test system, contactor, and reliability evaluation test method

An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NFor HF. A thermally decomposable reaction product produced as a result of the etching is removed by heat treatment.

Method of manufacturing a semiconductor device from which damage layers and native oxide films in connection holes have been removed

A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.

Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program

A stress analysis method is provided: including dividing, by using a division unit, an inside of a chip into a plurality of analysis areas, deriving, by using a composite property derivation unit, a composite property into which physical property values of a plurality of materials included in an analysis area are compounded, about each of the plurality of analysis areas on the basis of wiring structure data for each of the plurality of analysis areas, and creating, by using a stress analysis unit, a three-dimensional model of a finite element method which uses each analysis area as an element, to apply the composite property to each element, and to perform a stress analysis.

Stress analysis method, wiring structure design method, program, and semiconductor device production method

A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.

Semiconductor device including an insulating film and insulating pillars and manufacturing method of the semiconductor device

Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program product

A method for fabricating a semiconductor device, includes forming a first dielectric film above a substrate, forming an opening in the first dielectric film, forming a catalytic characteristic film using at least one of a metal having catalytic characteristics and a conductive oxide having catalytic characteristics as its material on sidewalls and at a bottom of the opening, depositing a conductive material film using a conductive material in the opening in which the catalytic characteristic film is formed on the sidewalls and at the bottom, removing the catalytic characteristic film formed on the sidewalls of the opening, and forming a second dielectric film above the first dielectric film and the conductive material film after the removing.

Method for fabricating semiconductor device

A method for fabricating a semiconductor device, includes forming an opening in a first film, embedding an alignment mark material for alignment with an upper layer in the opening, forming a second film on the first film in which the alignment mark material is embedded, irradiating the second film formed in a predetermined region including a position where the alignment mark material is embedded with a processing light, thereby to remove the second film to an extent that a portion of the second film remains in the predetermined region, and exposing the portion of the second film remaining in the predetermined region to an etching environment for etching the second film.

A method for manufacturing a semiconductor device includes forming, on a substrate having a recessed portion on a surface, a plating film which is at least buried in the recessed portion and has a higher impurity concentration in an upper portion than in a lower portion, thermally treating the plating film, and removing the thermally treated plating film except for a portion buried in the recessed portion.

Interconnect metallization method having thermally treated copper plate film with reduced micro-voids

A cathode potential is applied to a conductive layer formed on a substrate having a depression pattern. A plating solution in electrical contact with an anode is supplied to the conductive layer to form a plating film on the conductive layer. At this time, the plating solution is supplied by causing an impregnated member containing the plating solution to face the conductive layer. Since the plating solution stays in the depression, a larger amount of plating solution is supplied than on the upper surface of the substrate, and the plating rate of the plating film in the depression increases. Consequently, the plating film can be preferentially formed in the depression such as a groove or hole.

Plating method

A semiconductor device which is compact and thin in size, low in resistance of a current path and parasitic inductance and excellent in reliability is provided. This semiconductor device comprises a semiconductor substrate, a first main electrode which is formed on a front surface of the semiconductor substrate, a second main electrode which is formed on a rear surface of the semiconductor substrate, and a conducting portion which is formed in a direction to pierce through the semiconductor substrate, wherein the second main electrode is extracted to the front surface of the semiconductor substrate via the conducting portion. And, the conducting portion is a through via which has a through hole formed through the semiconductor substrate in its thickness direction and a conductive portion which is formed in the through hole and connected to the second main electrode.

Semiconductor device having power semiconductor elements

A method for manufacturing a semiconductor device includes forming a copper anti-diffusion film on a copper trench wiring layer, and forming an opening portion in the copper anti-diffusion film by laser ablation, the opening portion being formed in a region corresponding to an alignment region used for lithography process for forming an aluminum wiring on the copper trench wiring layer.

Method for manufacturing a semiconductor device

A plating method and apparatus for a substrate fills a metal, e.g., copper, into a fine interconnection pattern formed in a semiconductor substrate. The apparatus has a substrate holding portionhorizontally holding and rotating a substrate with its surface to be plated facing upward. A seal materialcontacts a peripheral edge portion of the surface, sealing the portion in a watertight manner. A cathode electrodepasses an electric current upon contact with the substrate. A cathode portionrotates integrally with the substrate holding portionAn electrode arm portionis above the cathode portionand movable horizontally and vertically and has an anodeface-down. Plating liquid is poured into a space between the surface to be plated and the anodebrought close to the surface to be plated. Thus, plating treatment and treatments incidental thereto can be performed by a single unit.

Method of performing electrolytic treatment on a conductive layer of a substrate

A method of manufacturing a semiconductor device according to an aspect of the present invention comprises forming a plated film on a substrate which has a recessed portion on its surface so as to bury in the recessed portion by a plating method; forming over the plated film a compressive stress-applying film which is composed of a material having a thermal expansion coefficient of 60% or less compared with a thermal expansion coefficient of a metal composing the plated film; heat-treating while applying a compressive stress to the plated film by the compressive stress-applying film; and removing the compressive stress-applying film and the plated film which is not buried in the recessed portion.

Method of manufacturing semiconductor device

Growing community of inventors

Fujisawa, Japan

Hisashi Kaneko