Mitsubishi Denki Kabushiki Kaisha

Hisao Kobashi

Yasuhiko Tsukikawa

Susumu Tanida

Mikio Sakurai

Tetsushi Hoshita

Takehiro Ochi

Yoshiyuki Hikiyama

During a burn-in test, a test mode signal TMRS is set to the H level, and word lines WL to WL can be activated by composite gates according to row address signals RA to RA , respectively. Therefore, a potential difference and a high electric field are provided even between word lines WL , WL during the burn-in test. Thus, the defect elimination rate during the burn-in test can be improved.

Semiconductor memory device with improved defect elimination rate

A redundancy row decoder in a DRAM includes a plurality of N channel MOS transistors connected in series between one terminal of each fuse and a line of a ground potential, the plurality of N channel MOS transistors having their gates receiving a predecode signal allocated to a corresponding word line. As compared with a conventional case where only one N channel MOS transistor is connected between one terminal of each fuse and the line of the ground potential, leakage current flowing through each fuse is made smaller.

Semiconductor memory device including spare memory cell

A clock buffer in a semiconductor memory device includes two kinds of interface circuits, i.e., an LVTTL interface and an SSTL interface. When the semiconductor memory device is set to a specific mode (self-refresh mode) for suppressing a power consumption, the LVTTL is used for taking in an external signal. In a mode other than the self-refresh mode, the SSTL interface is used to take in an externally supplied signal. Thereby, a current can be suppressed in the specific mode.

Semiconductor memory device provided with an interface circuit consuming

A switching circuit for switching a bit line potential VBL of a DRAM to a power supply potential Vcc, an intermediate potential Vcc/2 or the ground potential GND is provided. In normal operation, the bit line potential VBL is set to Vcc/2. In a special write mode, Vcc or GND is applied to all the bit lines through an equalizer, a desired word line is raised to 'H' level, and Vcc or GND is written to the storage nodes of all the memory cells connected to the word line. It is possible to write Vcc or GND even to the storage node of a memory cell which has been replaced by a redundant memory cell.

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Hyogo, Japan

Hisao Kobashi