Hitachi, Ltd.

Other

Texas Instruments Corporation

Hisao Asakura

Aritoshi Sugimoto

Yuichi Hamamura

Kazuyuki Tsunokuni

Takaaki Kumazawa

Ryo Nagai

Yoshitaka Tadaki

Toshihiro Sekiguchi

Norikatsu Takaura

Masayuki Nakamura

Masafumi Miyamoto

Riichiro Takemura

Satoru Yamada

Hideyuki Matsuoka

Shinichiro Kimura

Shinichi Miyatake

Jun Murata

Keizo Kawakita

Toshiyuki Kaeriyama

Songsu Cho

Yuji Ezaki

Shinya Nishio

Tsuyuki Suzuki

Masahiro Hyoma

Hideo Nagasawa

Fumiaki Saitoh

A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.

Method for test conditions

Photomask for test wafers

A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp and nw is L the width between active areas nwp and nw is L and the width between active areas nwp and nwp is L (L &minus;L ), (L &minus;L ), and (L &minus;L ) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L L and L can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.

Semiconductor integrated circuit device

System for testing electronic devices

Method of testing electronic devices

Method of testing electronic devices indicating short-circuit

The method of manufacturing a semiconductor integrated circuit device, which has an n-channel MIS transistor and a p-channel MIS transistor formed in the same semiconductor substrate, comprises ion implantation processes using the same photoresist as masks. The ion implantation processes include a step of injecting an impurity ion into the semiconductor substrate to form the source and drain of an n-channel MOSFET a p type semiconductor region for suppressing the short channel effect, and an n-well power supply region and a step of injecting an impurity ion into the semiconductor substrate to form the source and drain of a p-channel MOSFET an n type semiconductor region for suppressing the short channel effect, and a p-well power supply region

Semiconductor integrated circuit

Desired operating characteristics are obtained from an MISFET in which a p-type silicon gate electrode is used by preventing the leakage of boron into the channel region in the following way. N-type amorphous silicon is formed by ion-implanting phosphorus into an amorphous silicon. Next, boron is ion-implanted in n-type amorphous silicon to convert it into p-type amorphous silicon Amorphous silicon is then crystallized. Finally, the gate electrode of the MISFET is constructed of the p-type polycrystalline silicon, which has been obtained in the above steps, and in which phosphorus and boron have been implanted.

Process of manufacturing semiconductor integrated circuit device having an amorphous silicon gate

A mask for etching a relatively thin gate insulating film formed in a gate insulating film forming region is formed by patterning a photoresist film, and the mask is used for introducing an impurity for adjusting the threshold voltages of n-channel field-effect transistors and p-channel field-effect transistors having the relatively thin gate insulating film into regions on the semiconductor substrate not covered with the mask.

Method of fabricating semiconductor device

The method of manufacturing a semiconductor integrated circuit device, which has an n-channel MIS transistor and a p-channel MIS transistor formed in the same semiconductor substrate, comprises ion implantation processes using the same photoresist as masks. The ion implantation processes include a step of injecting an impurity ion into the semiconductor substrate,to form the source and drain of an n-channel MOSFET,a p type semiconductor region,for suppressing the short channel effect, and an n-well power supply region,and a step of injecting an impurity ion into the semiconductor substrate,to form the source and drain of a p-channel MOSFET,an n type semiconductor region,for suppressing the short channel effect, and a p-well power supply region

Semiconductor integrated circuit devices and a method of manufacturing the same

In a case where an impurity for suppressing the short channel effect of MISFETs is introduced into a semiconductor substrate obliquely to the principal surface thereof, gate electrodes adjacent to each other are arranged so that the impurity to be introduced in directions crossing the gate electrodes may not be introduced into the part of the semiconductor substrate lying between the gate electrodes, and the source region of the MISFETs is arranged in the part between the gate electrodes.

Method of manufacturing a semiconductor device, and semiconductor device

A method of making semiconductor devices which enables control of the impurity concentration and fine patterning by making removal of residual stress due LOCOS oxidation compatible with the formation of deep wells. A selective oxide layer is formed for separating element regions on a principal plane of a semiconductor substrate, for example, a p.sup.- -type silicon substrate 1. A mask is formed (for example photoresist 47) on the surface including the selective oxide layer and impurities (for example phosphorous) of a conductivity type opposite that of the semiconductor substrate are introduced via an opening in the mask. Then the selective oxide film is annealed by a high-temperature treatment while a deep well (for example n-type deep well 50) is formed by introducing the impurities.

Method of manufacturing semiconductor device

The method of manufacturing a semiconductor integrated circuit device, which has an n-channel MIS transistor and a p-channel MIS transistor formed in the same semiconductor substrate, comprises ion implantation processes using the same photoresist as masks. The ion implantation processes include a step of injecting an impurity ion into the semiconductor substrate 1 to form the source and drain of an n-channel MOSFET 3n, a p type semiconductor region 4p for suppressing the short channel effect, and an n-well power supply region 10n, and a step of injecting an impurity ion into the semiconductor substrate 1 to form the source and drain of a p-channel MOSFET 3p, an n type semiconductor region 4n for suppressing the short channel effect, and a p-well power supply region 10p.

CMOS device structure with reduced short channel effect and memory

Growing community of inventors

Tokyo, Japan

Hisao Asakura