Fujitsu Semiconductor Limited

Fujitsu Corporation

Fujitsu Microelectronics Limited

Sumco Techxiv Kabushiki Kaisha

Hiroyuki Ohta

Yosuke Shimamune

Naoyoshi Tamura

Akiyoshi Hatada

Akira Katakami

Masahiro Fukuda

Takashi Saiki

Katsuaki Ookoshi

Young Suk Kim

Hiroyuki Kanata

Hidekazu Satoh

Kenichi Okabe

Hidenobu Fukutome

Toshifumi Mori

Takashi Sakuma

Takashi Watanabe

Masashi Shima

Mitsuaki Hori

Kazuo Kawamura

Shinji Sugatani

Kengo Inoue

Koichi Shimomura

Mitsugu Tajima

Ryou Nakamura

Yasunori Iriyama

Yasuhiro Sambonsugi

Kimihiko Hosaka

Eiichirou Kotoura

Yoichi Morriyama

Hirotaka Takatsuka

A semiconductor device includes a transistor configuration including first and second gate electrodes, each of the first and second gate electrodes having at least a bottom layer and an upper layer including polycrystalline silicon grains, wherein the first gate electrode is a nMOS gate electrode formed in an nMOS region of the transistor configuration, wherein the polycrystalline silicon grains included in the bottom layer of the first gate electrode have a greater particle diameter than the polycrystalline grains included in the upper layer of the second gate electrode.

Semiconductor device and method of manufacturing the semiconductor device

The crucible and the side heater are held in the respective initial positions, and the raw material is put into the crucible. These initial positions are positions where the crucible side surface is mainly heated by the side heater. When the side heater heats the crucible side surface, the raw material is melted to form melt. When a part or all of the raw material is melted, the crucible is raised from the initial position or the side heater is lowered from the initial position. At this time, the position of the crucible or the side heater is adjusted such that the amount of heat applied to the lower side curved portion of the crucible side surface is greater than that in the initial relative position between the crucible and the side heater. And, if the crucible bottom part is heated by the side heater while the relative positions of the crucible and the side heater is maintained, the amount of heat applied to the crucible bottom part is increased as compared to the amount of heat applied to the crucible side surface, and the convection in the melt that makes the gas bubbles spatter to the outside. In this way, the gas bubbles are eliminated from the melt. As a result, the amount of gas bubbles in the melt can be reduced without deforming the crucible, and occurrence of pinhole defects in the wafer can be suppressed.

Method for melting semiconductor wafer raw material and crystal growing method for semiconductor wafer

A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.

Semiconductor device and method of manufacturing the same

A semiconductor device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a channel area formed in a silicon substrate, a gate electrode formed on a gate insulating film in correspondence with the channel area, and a source area and a drain area formed in the silicon substrate having the channel area situated therebetween. The PMOS transistor includes another channel area formed in the silicon substrate, another gate electrode formed on another gate insulating film in correspondence with the other channel area, and another source area and another drain area formed in the silicon substrate having the other channel area situated therebetween. The gate electrode has first sidewall insulating films. The other gate electrode has second sidewall insulating films. The distance between the second sidewall insulating films and the silicon substrate is greater than the distance between the first sidewall insulating films and the silicon substrate.

Method of forming semiconductor device having buffer layer between sidewall insulating film and semiconductor substrate

A semiconductor device including an n-channel MISFET including source/drain regionsformed in a semiconductor substratewith a channel region between them, and a gate electrodeof a metal silicide formed over the channel region with a gate insulating filminterposed therebetween; and an insulating filmformed over the gate electrodefrom side walls of the gate electrodeto an upper surface of the gate electrode, having a tensile stress from 1.0 to 2.0 GPa and applying the tensile stress to the channel region.

Semiconductor device and method for fabricating the same

A recess along a sidewall is formed in a pMOS region and an nMOS region. An SiC layer of which thickness is thicker than a depth of the recess is formed in the recess. A sidewall covering a part of the SiC layer is formed at both lateral sides of a gate electrode in the pMOS region. A recess is formed by selectively removing the SiC layer in the pMOS region. A side surface of the recess at the gate insulating film side is inclined so that the upper region of the side surface, the closer to the gate insulating film in a lateral direction at a region lower than the surface of the silicon substrate. An SiGe layer is formed in the recess in the pMOS region.

Semiconductor device and manufacturing method thereof

A semiconductor device has a first MOS transistor formed on first active region of the first conductivity type, having first gate electrode structure, first source/drain regions, recesses formed in the first source/drain regions, and semiconductor buried regions buried and grown on the recesses for applying stress to the channel under the first gate electrode structure, and a second MOS transistor formed on second active region of the second conductivity type, having second gate electrode structure, second source/drain regions, and semiconductor epitaxial layers formed on the second source/drain regions without forming recesses and preferably applying stress to the channel under the second gate electrode structure. In a CMOS device, performance can be improved by utilizing stress and manufacture processes can be simplified.

Method of manufacturing a semiconductor device including epitaxially growing semiconductor epitaxial layers on a surface of semiconductor substrate

A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.

Semiconductor device and production method thereof

A method for fabricating a semiconductor device includes the steps of: forming a first MISFET including first source/drain regions and a first gate electrode of a polycrystalline silicon, and a second MISFET including second source/drain regions and a second gate electrode of a polycrystalline silicon and having a gate length larger than that of the first gate electrode; and substituting the polycrystalline silicon forming the first and the second gate electrodes with a metal silicide. In the step of substituting the polycrystalline silicon with the metal silicide, the polycrystalline silicon forming the first gate electrode is totally substituted with the metal silicide and a part of polycrystalline silicon forming the second gate electrode is substituted with the metal silicide by utilizing that the gate length of the second gate electrode is larger than the gate length of the first gate electrode.

Method for fabricating semiconductor device with fully silicided gate electrode

Semiconductor device having buffer layer between sidewall insulating film and semiconductor substrate

A semiconductor device comprises a field-effect transistor arranged in a semiconductor substrate, which transistor has a gate electrode, source/drain impurity diffusion regions, and carbon layers surrounding the source/drain impurity diffusion regions. Each of the carbon layers is provided at an associated of the source/drain impurity diffusion regions and positioned so as to be offset from the front edge of a source/drain extension in direction away from the gate electrode and to surround as profile the associated source/drain impurity diffusion region.

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Kawasaki, Japan

Hiroyuki Ohta