International Business Machines Corporation

Applied Materials, Inc.

Globalfoundries Inc.

Zeon Corporation

Tokyo Electron Limited

Macronix International Co., Ltd.

Elpis Technologies Inc.

Hiroyuki Miyazoe

Takashi Ando

Eric Andrew Joseph

Robert L Bruce

Seyoung Kim

Michael A Guillorn

Marwan H Khater

Sebastian Ulrich Engelmann

Vijay Narayanan

Hsinyu Tsai

Gregory M Fritz

Nicholas C M Fuller

Josephine B Chang

Soon-Cheon Seo

Markus Brink

Nathan P Marchack

Youngseok Kim

Cyril Cabral, Jr

Dexin Kong

Mark Hoinkis

Iqbal Rashid Saraf

Adam M Pyzyna

Kumar R Virwani

Kenneth Parker Rodbell

Martin Michael Frank

Anthony J Annunziata

Eduard Albert Cartier

Masahiro Nakamura

Shyng-Tsong Chen

Teddie Peregrino Magbitang

Chun Yan

John Rozen

Benjamin L Fletcher

Ghavam G Shahidi

Steven J Holmes

Reinaldo Ariel Vega

Joel Pereira De Souza

Joshua T Smith

Chandrasekharan Kothandaraman

Cheng-Wei Cheng

Ratnam Sooriyakumaran

Wu-Song S Huang

Babar Ali Khan

Chi-Chun Liu

Rajasekhar Venigalla

Kafai Lai

Willi Volksen

Michael F Lofaro

Aaron Daniel Franklin

Martin Glodde

Hari V Mallela

Geraud J Dubois

Satoshi Oida

Qingyun Yang

HsinYu Tsai

Brian A Bryce

Asit Kumar Ray

Brett Caroline Baker-O'Neal

Ashish V Jagtiani

Devi Koty

Gloria W Y Fraczak

Jeffrey W Sleight

Michael S Gordon

Alfred Grill

Christopher Vincent Jahnes

Eugene John O'Sullivan

Qing Cao

Sri Muthuthamby Sri-Jayantha

Damon B Farmer

Deborah A Neumayer

Paul Charles Jamison

John Christopher Arnold

Nicole A Saulnier

Arun Sharma

Hongwen Yan

Sanghoon Lee

Jeffrey C Shearer

Huai-Yu Cheng

Fabio Carta

John M Papalia

Karthik Yogendra

I-Ting Kuo

Rohit Kilaru

Takefumi Suzuki

Marinus Johannes Petrus Hopstaken

Bang N To

Gloria W Fraczak

Matthew Peter Sagianis

Leonidas Ernesto Ocola

Gloria Wing Yun Fraczak

Luxherta Buzi

Sebastian Ulrich Englemann

A method of fabricating a resistive semiconductor memory structure that provides in-situ selective etch of phase change materials during deposition of dielectric at low temperature (in the same chamber). The method provides, to a single processing chamber, a semiconductor wafer including a trimmed resistive memory device structure having one or more layers of phase change material used to form a resistive memory device. The one or more layers of phase change material have oxidized sidewall surfaces as a result of a prior etching step where a whole stack structure of the layers forming the resistive memory structure is etched. Then, an encapsulating of the trimmed resistive memory device structure is performed by depositing, within the processing chamber, using a PECVD, a layer of dielectric material, and during the encapsulating, etching, within the processing chamber, the wafer to selectively remove the phase change material oxidation at the sidewall surfaces.

In-situ low temperature dielectric deposition and selective trim of phase change materials

A resistive memory includes: a bottom electrode; a first contact on the bottom electrode; a switching material pad on the first contact, wherein the switching material pad includes an oxide and a plurality of current conducting filaments in the oxide; a top electrode on the switching material pad; a plurality of sacrificial vias contacting the bottom electrode; a second contact that is connected to the bottom electrode; and a third contact that is connected to the top electrode.

Redundant bottom pad and sacrificial via contact for process induced RRAM forming

Embodiments of present invention provide a method of forming a resistive random-access memory (RRAM). The method includes forming a dielectric layer on top of a supporting structure, wherein the dielectric layer has a bottom electrode embedded therein; forming an oxide layer on top of the bottom electrode; treating the oxide layer in a plasma environment; forming a top electrode on top of the oxide layer; forming a first interlevel-dielectric (ILD) layer on top of the top electrode; forming a via contact and a first metal layer in the first ILD layer, wherein the first metal layer is in contact with the top electrode through the via contact; forming a capping layer on top of the first metal layer through a plasma-enhanced deposition process; and causing formation of one or more filaments in the oxide layer during the plasma-enhanced deposition process. A structure of the RRAM is also provided.

Process-induced forming of oxide RRAM

A semiconductor device including stacked access device and resistive memory includes a stack disposed on a base structure, the stack including an access device stack and a resistive random-access memory (ReRAM) device stack, sidewall spacers disposed along a portion of the stack, a dielectric layer disposed over the stack, the sidewall spacers and the base structure, and an interlevel dielectric disposed on the dielectric layer.

Stacked access device and resistive memory

Embodiments of the invention provide a resistive switching device that includes a metal interconnect electrode and a charge-particle-treated memory stack over the metal interconnect electrode. The charge-particle-treated memory stack includes a plurality of layers that includes a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode. The dielectric layer includes a portion of a blanket dielectric layer. The bottom electrode includes a portion of a blanket bottom electrode layer. The charge-particle-treated memory stack further includes a current-conducting filament characteristic that results from charge particle treatments applied while a top surface of the blanket dielectric layer is exposed and a top surface of the blanket bottom electrode is exposed.

Oxide-based resistive memory having a plasma-exposed bottom electrode

Structures and methods are provided for integrating a resistance random access memory (ReRAM) in a back-end-on-the-line (BEOL) fat wire level. In one embodiment, a ReRAM device area contact structure is provided in the BEOL fat wire level that has at least a lower via portion that contacts a surface of a top electrode of a ReRAM device area ReRAM-containing stack. In other embodiments, a tall ReRAM device area bottom electrode is provided in the BEOL fat wire level and embedded in a dielectric material stack that includes a dielectric capping layer and an interlayer dielectric material layer.

BEOL fat wire level ground rule compatible embedded artificial intelligence integration

A porous thin film includes a framework that includes a plurality of pores. The pores extend from an opening located at an upper surface of the framework to a bottom surface contained in the framework. A pore-coating film is formed on sidewalls and the bottom surface of the pores.

Percolation doping of inorganic-organic frameworks for multiple device applications

A method for mitigating moisture driven degradation of silicon doped chalcogenides includes placing a silicon doped chalcogenide composition in a process chamber, passivating dangling silicon bonds of the silicon doped chalcogenide composition by flooding the process chamber with forming gas or with hydrogen plasma, purging the forming gas or the hydrogen plasma from the process chamber, and removing the passivated silicon doped chalcogenide composition from the process chamber.

Mitigating moisture driven degradation of silicon doped chalcogenides

Embodiments of process flows and methods are provided for forming a resistive switching random access memory (ReRAM). More specifically, process flows and methods are provided for reducing the forming voltage needed to form a conductive path in the ReRAM cells. A wide variety of plasma doping processes are used to introduce a plurality of different dopants into a metal-oxide dielectric film. By utilizing at least two different dopants, the plasma doping processes described herein reduce the forming voltage of the subsequently formed ReRAM cell compared to conventional processes that use only one dopant. In some embodiments, the forming voltage may be further reduced by applying a bias power during the plasma doping process, wherein the bias power is preselected to increase the number of ions introduced into the metal-oxide dielectric film during the plasma doping process.

Plasma co-doping to reduce the forming voltage in resistive random access memory (ReRAM) devices

Techniques facilitating resistive random-access memory device with step height difference are provided. A resistive random-access memory device can comprise a first electrode located within a trench of a dielectric layer. The resistive random-access memory device can also comprise a metal oxide layer comprising a first section located within the trench of the dielectric layer, and a second section located over the first electrode, and over a barrier metal layer. Further, the resistive random-access memory device can comprise a second electrode located over the metal oxide layer.

Resistive random-access memory device with step height difference

A method for manufacturing a semiconductor memory device includes depositing a bottom metal line layer on a dielectric layer, and patterning the bottom metal line layer into a plurality of bottom metal lines spaced apart from each other. In the method, a plurality of switching element dielectric portions are formed on respective ones of the plurality of bottom metal lines, and a top metal line layer is deposited on the plurality of switching element dielectric portions. The method further includes patterning the top metal line layer into a plurality of top metal lines spaced apart from each other. The plurality of top metal lines are oriented perpendicular to the plurality of bottom metal lines.

Conductive bridging random access memory formed using selective barrier metal removal

Provided are embodiments for a semiconductor device. The semiconductor device includes a bottom electrode, wherein the bottom electrode is formed on a metal interconnect electrode, and a dielectric layer on a surface of the bottom electrode. The semiconductor device also includes a top electrode formed on a surface of the dielectric layer, wherein at least one of the top electrode or the bottom electrode is a plasma treated top electrode or plasma treated bottom electrode. Also provided are embodiments for a method of fabricating a resistive switching device where at least one of the plurality of layers of the memory stack is processed with a charge particle treatment.

A low voltage forming NVM structure including a plurality of ReRAM devices arranged in a cross bar array and sandwiched between a plurality of first electrically conductive structures and a plurality of second electrically conductive structures. Each first electrically conductive structure is oriented perpendicular to each second electrically conductive structure. The plurality of second electrically conductive structures includes a first set of second electrically conductive structures having a first top trench area A, and a second set of second electrically conductive structures having a second top trench area Athat is greater than A. Each second electrically conductive structure of the first set contacts a surface of at least one of the first electrically conductive structures, and each second electrically conductive structure of the second set contacts a top electrode of at least one of the ReRAM devices.

Non-volatile memory structure and method for low programming voltage for cross bar array

Semiconductor memory devices formed using selective barrier metal removal

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White Plains, NY, United States of America

Hiroyuki Miyazoe