Fujitsu Corporation

Cypress Semiconductor Corporation

Fujitsu Semiconductor Limited

Hiroyuki Matsunami

Koji Okada

Osamu Yamaguchi

Suguru Tachibana

Kazuhiro Tomita

Kouji Okada

Kazuyoshi Futamura

Yasukazu Ono

Masashi Kijima

Satoru Mizuta

Tsutomu Tanii

Yukinobu Tanida

Masahiro Tanaka

Osamu Sugaya

A device includes a master delay-lock loop (DLL) having a phase frequency detector connected in series with a charge pump that is to generate a control voltage. A slave DLL is coupled to the master DLL and has a delay line including a buffer to receive a slave clock and a series of delay cells coupled between the buffer and an output terminal that is to output a delay clock, the series of delay cells variably controlled by the control voltage. The master DLL and the slave DLL are powered by a power supply that experiences undershoot or overshoot in response to a load transient. A dummy load is coupled between the delay line of the slave DLL and an output of the power supply, the dummy load including an exclusive OR gate that receives, as inputs, a first output of the buffer and the delay clock.

Reducing delay-lock loop delay fluctuation

In an example embodiment, an analog-digital converter includes digital-analog converter, a comparator, and a register. The digital-analog converter is configured to output a differential voltage between a reference voltage and a voltage of an analog signal. The comparator is configured to output a comparison signal corresponding to the differential voltage output by the digital-analog converter. The register is configured to cause the digital-analog converter to generate N pairs of differential voltages (N&#x2267;1), to cause the digital-analog converter to generate an (N+1)pair of differential voltages by causing one of a positive side and a negative side of the digital-analog converter to output an (N+1)differential voltage and causing the other of the positive side and the negative side to output a differential voltage equal to the Ndifferential voltage as an (N+1)differential voltage, and to output a digital signal corresponding to a comparison signal having a smallest voltage among (N+1) comparison signals.

Analog-digital converter and control method

An adjusting apparatus sets a designated value of a current source circuit to be a predetermined value, and causes discharging of a capacitor to end by switching a switch to a discharging side when the capacitor is not being charged by current output from a switching power source circuit. After the discharging of the capacitor ends and the designated value is set, the adjusting apparatus causes the capacitor to be charged by switching the switch to a charging side. The adjusting apparatus further measures a time period from the time when the switch is switched to the charging side until an electric potential difference of the capacitor exceeds a threshold value. Based on the measured time period and the predetermined value, the adjusting apparatus calculates the designated value such that the measured time period is a predetermined time period.

Adjusting apparatus and adjustment method

A reference voltage circuit includes a first amplifier, a first load device and a first PN junction device, second and third load devices and a second PN junction device, an offset voltage reduction circuit, a coupling node potential takeout circuit, and an area adjustment circuit. The offset voltage reduction circuit is configured to reduce an offset voltage between the first and second input terminals at the first amplifier, and the coupling node potential takeout circuit is configured to take out potentials of the first and second coupling nodes. The area adjustment circuit is configured to adjust an area of the second PN junction device in accordance with the potentials of the first and second coupling nodes which are taken out by the coupling node potential takeout circuit.

Reference voltage circuit and semiconductor integrated circuit

A variable delay circuit comprising a first delay element configured to delay an input signal, a second delay element coupled to the first delay element in parallel and also configured to delay the input signal, a control current supply section configured to supply control currents for adjusting a delay amount of the first delay element and a delay amount of the second delay element, and an output signal selecting section configured to select any one of an output signal from the first delay element and an output signal from the second delay element according to a selecting signal for selecting delay time of the input signal.

Variable delay circuit and delay amount control method

A control signal that runs a control oscillator of a signal generation circuit that generates a write clock is taken as a reference signal. That reference signal is supplied to a signal generation circuit that generates a read clock. In the signal generation circuit that generates the read clock, there is no need to generate a reference signal within its own circuits, which makes it possible to supply it to a control oscillator by adding the error timing from reading out the signal against the supplied reference signal. In this way, no means for locking the read clock into the initial frequency is needed and neither is the time for locking the read clock to the initial frequency (lock up time). This makes it possible to reduce the size of the circuit and to reduce the signal read-out time.

Signal generating circuit, timing recovery PLL, signal generating system and signal generating method

To present a clock generator capable of spreading the spectrum of oscillation frequency by simple control in a small additional circuit, and its control method. A phase locked loop circuit is provided from a frequency phase comparator, an output clock signal PO is outputted from a voltage control oscillator (VCO)by way of a charge pump circuit (CP)and a loop filter (LF), and is returned to the frequency phase comparatorby way of a frequency divider (DIV). Detecting the phase difference of reference clock signal R and divided clock signal D, and locking the oscillation frequency of the output clock signal PO to specified frequency, a modulation signal M is outputted from a modulation pulse generatorregardless of phase locked control of phase locked loop circuit, and is superposed on phase comparison signal P, and thereby the oscillation frequency of output clock signal PO is modulated. An output clock signal PO having a predetermined spectrum spread characteristic can be obtained.

Clock generator and its control method

An object of this invention is to provide a band distribution inspecting device and band distribution inspecting method capable of carrying out inspection on whether or not a scattered oscillation signal oscillated containing a frequency variation from the fundamental frequency with the fundamental frequency as a reference point has a band distribution rapidly, with a simple way and at a cheap price. A scattered oscillation signal SSS inputted to a band distribution detecting sectionis outputted as a predetermined band pass signal SBP through a band pass filterhaving a predetermined pass band of a predetermined narrow-band width &#x394;f within a band distribution. This signal is converted to a root-mean-square value by a smoother, smoothed by a capacitor Cand transferred to a general purpose inspecting deviceas a DC signal SAV. The DC signal SAV is compared with a predetermined voltage value VX by a comparatorand its comparison result is judged by a judging sectionand then, an inspection result is outputted as a judging signal J. As a result, an edge frequency in the band distribution of the scattered oscillation signal SSS and disturbance of frequency variation within/out of the band and dullness in waveform and the like can be inspected for.

Band distribution inspecting device and band distribution inspecting method

A Digital/Analog converter comprising a plurality of current sources, and a selecting circuit for selecting a current source from the plurality of current sources on the basis of a digital signal. The selecting circuit includes a first transistor in which the digital signal is supplied. The selecting circuit also includes a second transistor with the same conductivity type as the first transistor for receiving an inverted digital signal of the digital signal. The second transistor is connected to the output of the first transistor.

Growing community of inventors

Kasugai, Japan

Hiroyuki Matsunami