Renesas Electronics Corporation

Nec Electronics Corporation

Renesas Electronics Coporation

Hiroyuki Kobatake

Noriaki Kodama

Takuji Onuma

Kenichi Hidaka

A capacitance coupled to a memory node and a word line of an SRAM cell provides an electrostatic capacitance between the memory node and the word line. The capacitance has a first electrostatic capacitance when the word line is in a nonselective state (usually a LOW level) and the memory node retains a HIGH level; the capacitance has a second electrostatic capacitance which is smaller than the first electrostatic capacitance when the word line is in the nonselective state (usually the LOW level) and the memory node retains the LOW level.

Semiconductor device having memory cell with electrostatic capacitance circuit

Provided is a semiconductor storage device including first and second load transistors, first and second drive transistors, first and second transfer transistors, and first and second cell node lines each serving as a storage node. A portion where a cell node line and a bit line corresponding to the cell node line overlap each other when viewed from above is formed between the cell node line and the bit line.

Semiconductor storage device

A semiconductor device is provided with a lower-layer circuit including a transistor formed over a semiconductor substrate, and a memory cell array formed in an interconnection layer above the semiconductor substrate. Respective memory cells of the memory cell array are provided with a variable resistor element formed in the interconnection layer serving as a memory element. The memory cell array includes a first region directly underneath the memory cells, the first region being a region where a via for electrical coupling with the memory cell is not formed. The lower-layer circuit is disposed in such a way as to overlap at least a part of the first region.

Semiconductor device

A non-volatile semiconductor memory device having a memory cell in which operating potentials are few and the scale of the peripheral circuitry is reduced includes a select transistor having a source/drain on both sides of a channel of a semiconductor substrate and having a gate electrode disposed on the channel via a thick gate insulating film; an element isolation region formed on the semiconductor substrate in an area adjacent to the select transistor; an antifuse adjacent to the element isolation region, having a lower electrode formed on the semiconductor substrate and having an upper electrode disposed on the semiconductor substrate in an area between the element isolation region and lower electrode via a thin gate insulating film; and a connection contact electrically connecting the source and upper electrode and contacting the source and the upper electrode.

Non-volatile semiconductor memory device

A test circuit includes a signal level modifying circuit. The signal level modifying circuit modifies at least one of signal levels of an inverting input signal and a noninverting input signal supplied to a differential input circuit in response to a test signal outputted from a signal output circuit to make a difference between signal levels of the inverting input signal and the noninverting input signal smaller than that in a normal operation. Here, the test signal indicates a test mode in which input/output characteristics of the differential input circuit is tested.

Test circuit and test method for testing differential input circuit

A method of testing a static random access memory (SRAM), the method including writing a data into the SRAM cell to store a first potential level at a first node and a second potential level greater than the first potential level at a second node, supplying a power supply voltage from a power supply terminal to first and second bit lines by activating first and second transistors and deactivating first and second transfer gates, and supplying the power supply voltage to the first bit line by activating the first transistor and activating the first and second transfer gates.

Static random access memory (SRAM) and test method of the SRAM having precharge circuit to prepcharge bit line

An SRAM includes a memory cell and a precharge circuit. The precharge circuit precharges a bit line pair with a power supply voltage before writing a data in the memory cell or before reading a data therefrom at a time of a normal mode, and which feeds a power supply voltage to at least a low level data-holding node of a node pair of the memory cell at a time of a read test mode, between time for writing a data in the memory cell and time for reading a data therefrom.

Static random access memory (SRAM) and test method of the SRAM having precharge circuit to precharge bit line

The differential sense amplifier according to one aspect of the present invention includes a first differential amplification unit that detects a difference between the pair of complementary signals inputted from a first bit line and a second bit line, a second differential amplification unit that detects a difference between one of the complementary signals inputted from the first bit line and a first reference signal, and a third differential amplification unit that detects a difference between the other complementary signal inputted from the second bit line and a second reference signal.

Differential sense amplifier

Provided is a semiconductor integrated circuit including: a first path that includes a first logic circuit; a second path that includes a second logic circuit; and a subsequent-stage circuit that is connected to an output of the first path and is connected to an output of the second path, in which the second path further includes a first internal path that is selected as a propagation path during a normal operation period; and a second internal path that is selected as a propagation path during a test operation period and includes a delay circuit having a delay amount larger than a delay amount of the first internal path.

Semiconductor integrated circuit and method of testing the same

A semiconductor storage device in accordance with an exemplary aspect of the present invention includes a plurality of memory cells arranged in a matrix pattern, a plurality of word lines each provided so as to correspond to each line of the memory cells, a plurality of bit lines each connected to respective one of the memory cells, and a row selection circuit that, in a read operation, drives the word line to a set potential at a drive speed slower than a discharge speed of the bit line exhibited when the word line is raised roughly vertically to VDD.

An SRAM includes a memory cell; and a control circuit configured to change a signal level of a signal which is used in an ordinary mode for access to the memory cell in a test mode to apply a disturbance to the memory cell. The control circuit can change the signal level to set a level of the disturbance optionally.

SRAM and testing method of SRAM

A fuse data read circuit includes a fuse data holding unit which holds fuse data, a fuse data read unit which detects fuse data, and a bias voltage generating circuit which generates a bias voltage. The fuse data read unit includes a current mirror circuit and a control circuit provided between the current mirror circuit and the fuse data holding unit. The bias voltage generating circuit applies the bias voltage to the control circuit.

Fuse data read circuit having control circuit between fuse and current mirror circuit

A semiconductor integrated circuit device includes: a plurality of memories and a judgement circuit. Each of plurality of memories is configured to include a Built-in Self Test (BIST) circuit that examines a possibility of repairing a defect and outputs a repair possibility signal indicating the possibility. The judgement circuit is configured to judge whether or not all of the plurality of memories can be repaired based on a plurality of the repair possibility signals. Each of the plurality of the repair possibility signals is outputted from one of the plurality of memories.

Growing community of inventors

Kanagawa, Japan

Hiroyuki Kobatake